remove use_reg on compiler and SA for load

This commit is contained in:
2020-02-29 17:17:58 +02:00
parent 0ce14bdfd1
commit 77003eed06
3 changed files with 42 additions and 8 deletions

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@ -51,12 +51,6 @@ module Risc
self
end
# require a (temporary) register. code must give this back with release_reg
# Second extra parameter may give extra info about the value, see RegisterValue
def use_reg( type , extra = {} )
@allocator.use_reg(type, extra)
end
# resolve the type of the slot, by inferring from it's name, using the type
# scope related slots are resolved by the compiler by method/block
def slot_type( slot , type)