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fix operator register usage

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which makes inter math work
surprise!
This commit is contained in:
Torsten 2020-03-25 18:38:32 +02:00
parent bc558d1f0d
commit 7572e27869
2 changed files with 12 additions and 8 deletions
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3
.gdbinit Normal file
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@ -0,0 +1,3 @@
set disassemble-next-line on
file a.out
break *0x10054

15
lib/arm/translator.rb
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@ -93,21 +93,22 @@ module Arm
def translate_OperatorInstruction( code )
left = code.left
right = code.right
result = code.result
case code.operator.to_s
when "+"
c = ArmMachine.add(left , left , right)
c = ArmMachine.add(result , left , right)
when "-"
c = ArmMachine.sub(left , left , right)
c = ArmMachine.sub(result , left , right)
when "&"
c = ArmMachine.and(left , left , right)
c = ArmMachine.and(result , left , right)
when "|"
c = ArmMachine.orr(left , left , right)
c = ArmMachine.orr(result , left , right)
when "*"
c = ArmMachine.mul(left , right , left) #arm rule about left not being result, lukily commutative
c = ArmMachine.mul(result , right , left) #arm rule about left not being result, lukily commutative
when ">>"
c = ArmMachine.mov(left , left , :shift_asr => right) #arm rule about left not being result, lukily commutative
c = ArmMachine.mov(result , left , :shift_asr => right) #arm rule about left not being result, lukily commutative
when "<<"
c = ArmMachine.mov(left , left , :shift_lsl => right) #arm rule about left not being result, lukily commutative
c = ArmMachine.mov(result , left , :shift_lsl => right) #arm rule about left not being result, lukily commutative
else
raise "unimplemented '#{code.operator}' #{code}"
end