operator also fell into ssa trap
relying on register identity in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue better now
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@ -192,7 +192,7 @@ module Risc
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right = right.to_reg() if(right.is_a?(RegisterSlot))
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ret = Risc.op( "operator #{operator}" , operator , self , right , result)
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compiler.add_code(ret) if compiler
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ret
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ret.result
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end
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# just capture the values in an intermediary object (RegisterSlot)
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@ -13,8 +13,8 @@ module SlotMachine
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builder.build do
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integer = message[:receiver].reduce_int(false)
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integer_reg = message[:arg1].reduce_int(false)
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integer.op operator , integer_reg
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integer_tmp[Parfait::Integer.integer_index] << integer
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result = integer.op operator , integer_reg
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integer_tmp[Parfait::Integer.integer_index] << result
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message[:return_value] << integer_tmp
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end
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return compiler
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@ -51,11 +51,15 @@ module Risc
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assert_equal @r0 , message.register
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end
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def test_operator
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ret = @r0.op :<< , @r1
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@r0.set_compiler( fake = SuperFakeCompiler.new)
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result = @r0.op :<< , @r1
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ret = fake.code
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assert_operator ret , :<< , :message , "id_" , "op_<<_"
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end
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def test_operator_slot
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ret = @r0.op :<< , @r1[:type]
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@r0.set_compiler( fake = SuperFakeCompiler.new)
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result = @r0.op :<< , @r1[:type]
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ret = fake.code
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assert_operator ret , :<< , :message , "id_.type" , "op_<<_"
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end
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def test_byte_to_reg
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@ -41,7 +41,7 @@ module SlotMachine
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assert_slot_to_reg s + 3 ,:message , 9 , "message.arg1"
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assert_slot_to_reg s + 4 , "message.arg1" , 2 , "message.arg1.data_1"
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assert_operator s + 5 , :| , "message.receiver.data_1" , "message.arg1.data_1" , "op_|_"
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assert_reg_to_slot s + 6 , "message.receiver.data_1" , "id_factory_.next_object" , 2
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assert_reg_to_slot s + 6 , "op_|_" , "id_factory_.next_object" , 2
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assert_reg_to_slot s + 7 , "id_factory_.next_object" , :message , 5
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assert_slot_to_reg s + 8 ,:message , 5 , "message.return_value"
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assert_reg_to_slot s + 9 , "message.return_value" , :message , 5
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