operator also fell into ssa trap

relying on register identity
in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue
better now
This commit is contained in:
2020-03-15 12:58:16 +02:00
parent 3145547315
commit 7232c28ecd
4 changed files with 10 additions and 6 deletions

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@ -192,7 +192,7 @@ module Risc
right = right.to_reg() if(right.is_a?(RegisterSlot))
ret = Risc.op( "operator #{operator}" , operator , self , right , result)
compiler.add_code(ret) if compiler
ret
ret.result
end
# just capture the values in an intermediary object (RegisterSlot)