operator also fell into ssa trap
relying on register identity in fact the whole operator concept was geared towards this, using 2 regs instead of one to avoid the whole issue better now
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@ -192,7 +192,7 @@ module Risc
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right = right.to_reg() if(right.is_a?(RegisterSlot))
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ret = Risc.op( "operator #{operator}" , operator , self , right , result)
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compiler.add_code(ret) if compiler
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ret
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ret.result
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end
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# just capture the values in an intermediary object (RegisterSlot)
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