working on registers, awip (a work in progress)

This commit is contained in:
Torsten Ruger
2014-05-25 08:43:07 +03:00
parent 1e326e00b9
commit 6ac92cac3a
9 changed files with 80 additions and 40 deletions

View File

@ -10,6 +10,10 @@ require_relative "constants"
module Arm
class ArmMachine < Vm::RegisterMachine
def integer_equals block , left , right
block << cmp( left , right )
Vm::BranchCondition.new :eq
end
def integer_less_or_equal block , left , right
block << cmp( left , right )
Vm::BranchCondition.new :le

View File

@ -12,6 +12,10 @@ module Arm
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
raise inspect if to.is_a?(Vm::Value) and
from.is_a?(Vm::Value) and
!@attributes[:shift_lsr] and
to.register == from.register
end
# arm intrucions are pretty sensible, and always 4 bytes (thumb not supported)