some more addresses

This commit is contained in:
Torsten Ruger
2018-07-15 15:13:25 +03:00
parent eaeea29e38
commit 69385c863f
5 changed files with 6 additions and 6 deletions

View File

@ -45,7 +45,7 @@ module Risc
ret = main_ticks(63)
assert_equal FunctionReturn , ret.class
assert_equal :r1 , ret.register.symbol
assert_equal 21732 , @interpreter.get_register(ret.register)
assert_equal 23332 , @interpreter.get_register(ret.register)
end
def test_sys
sys = main_ticks(68)

View File

@ -54,7 +54,7 @@ module Risc
end
def test_pc1
@interpreter.tick
assert_equal 21304 , @interpreter.pc
assert_equal 22904 , @interpreter.pc
end
def test_tick2
@interpreter.tick
@ -68,7 +68,7 @@ module Risc
def test_pc2
@interpreter.tick
@interpreter.tick
assert_equal 21308 , @interpreter.pc
assert_equal 22908 , @interpreter.pc
end
def test_tick_14_jump
14.times {@interpreter.tick}

View File

@ -25,7 +25,7 @@ module Risc
assert_equal 0 , Position.get(@linker.cpu_init).at
end
def test_cpu_at
assert_equal "0x61ec" , Position.get(@linker.cpu_init.first).to_s
assert_equal "0x682c" , Position.get(@linker.cpu_init.first).to_s
end
def test_cpu_label
assert_equal Position , Position.get(@linker.cpu_init.first).class