diff --git a/lib/risc/register_value.rb b/lib/risc/register_value.rb
index 916aea20..8fe6954c 100644
--- a/lib/risc/register_value.rb
+++ b/lib/risc/register_value.rb
@@ -30,6 +30,10 @@ module Risc
       @extra = extra
     end
 
+    def class_name
+      return :fixnum unless @type
+      @type.class_name
+    end
     # using the registers type, resolve the slot to an index
     # Using the index and the register, add a SlotToReg to the instruction
     def resolve_and_add(slot , instruction , compiler)
@@ -66,7 +70,7 @@ module Risc
     end
 
     def to_s
-      s = "#{symbol}:#{type&.class_name}"
+      s = "#{symbol}:#{class_name}"
       s += ":#{extra}" unless extra.empty?
       s
     end
@@ -171,7 +175,7 @@ module Risc
     # itself (the slot) and the register given
     def <<( reg )
       raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
-      reg_to_slot = Risc.reg_to_slot("#{reg.type.class_name} -> #{register.type.class_name}[#{index}]" , reg , register, index)
+      reg_to_slot = Risc.reg_to_slot("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
       builder.add_code(reg_to_slot) if builder
       reg_to_slot
     end
diff --git a/test/risc/test_register_value.rb b/test/risc/test_register_value.rb
index b8c8c815..77c5a523 100644
--- a/test/risc/test_register_value.rb
+++ b/test/risc/test_register_value.rb
@@ -14,6 +14,12 @@ module Risc
       @r0 = RegisterValue.new(:r0 , :Message)
       @r1 = RegisterValue.new(:r1 , :Space)
     end
+    def test_class_name_type
+      assert_equal :Message , @r0.class_name
+    end
+    def test_class_name_fix
+      assert_equal :fixnum , RegisterValue.new(:r0 , :fixnum).class_name
+    end
     def test_r0
       assert_equal :r0 , @r0.symbol
     end