fix mom and vool after cc changes

This commit is contained in:
2019-08-23 10:21:22 +03:00
parent ec1e8c8f3a
commit 5e44e9caaf
16 changed files with 50 additions and 64 deletions

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@ -7,9 +7,7 @@ module Risc
def setup
super
@input = "local = arg; return local"
@expect =[ SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #4
RegToSlot, Branch] #9
@expect = [SlotToReg, RegToSlot, SlotToReg, RegToSlot, Branch] #4
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -26,8 +24,8 @@ module Risc
end
def test_load_frame_from_message
produced = produce_body
assert_equal :r3 , produced.next(2).array.symbol , produced.next.to_rxf[0..200]
assert_equal 3 , produced.next.index , produced.next.to_rxf[0..200]
assert_equal 16 , produced.next.index , produced.next.to_rxf[0..200]
assert_equal :r0 , produced.next(2).array.symbol
end
end
end

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@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "r = false;return"
@expect = [LoadConstant,SlotToReg, RegToSlot,LoadConstant, RegToSlot, Branch]
@expect = [LoadConstant, RegToSlot,LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -21,12 +21,12 @@ module Risc
def test_frame_load
produced = produce_body
assert_equal :Message , produced.next(1).array.type.class_name
assert_equal 3 , produced.next(1).index # 3 is frame
assert_equal 16 , produced.next(1).index # 3 is frame
end
def test_value_load
produced = produce_body
assert_equal produced.next(2).register , produced.register
assert_equal 1 , produced.next(2).index #type == 0 , r == 1
assert_equal 16 , produced.next(1).index #type == 0 , r == 16
end
end

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@ -7,7 +7,7 @@ module Risc
def setup
super
@input = "r = 5;return"
@expect = [LoadConstant,SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
@expect = [LoadConstant, RegToSlot, LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg
@ -21,12 +21,11 @@ module Risc
def test_frame_load
produced = produce_body
assert_equal :Message , produced.next(1).array.type.class_name
assert_equal 3 , produced.next(1).index # 4 is frame
assert_equal 16 , produced.next(1).index # 4 is frame
end
def test_value_load
produced = produce_body
assert_equal produced.next(2).register , produced.register
assert_equal 1 , produced.next(2).index #type == 1 , r == 2
assert_equal produced.next(1).register , produced.register
end
end

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@ -7,8 +7,8 @@ module Risc
def setup
super
@input = "@ivar = 5 ; r = @ivar;return"
@expect = [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg ,
RegToSlot, LoadConstant, RegToSlot, Branch]
@expect = [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #4
RegToSlot, LoadConstant, RegToSlot, Branch] #9
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -7,11 +7,11 @@ module Risc
def setup
super
@input = "r = 5.div4;return"
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, Branch]
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot, #4
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, #9
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #14
FunctionCall, Label, SlotToReg, RegToSlot, LoadConstant, #19
RegToSlot, Branch] #2
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg