Fixing tests for implicit return
previous commit affected rather many test, as the implicit returns add extra instructions Also added some explicit returns, so as not to test the return logic too much. return (ie return nl) is a knonwn 3 risc operation.
This commit is contained in:
@ -6,8 +6,8 @@ module Risc
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def setup
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super
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@input = "arg = 5"
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@expect = [LoadConstant, SlotToReg, RegToSlot]
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@input = "arg = 5;return"
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@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -6,8 +6,8 @@ module Risc
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def setup
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super
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@input = "@ivar = 5"
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@expect = [LoadConstant, SlotToReg, RegToSlot]
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@input = "@ivar = 5;return"
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@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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@ -6,8 +6,9 @@ module Risc
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def setup
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super
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@input = "local = arg"
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@expect = [SlotToReg, SlotToReg, SlotToReg, RegToSlot]
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@input = "local = arg; return local"
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@expect = [SlotToReg, SlotToReg, SlotToReg, RegToSlot, SlotToReg, #4
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SlotToReg, RegToSlot, Branch] #9
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -6,8 +6,8 @@ module Risc
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def setup
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super
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@input = "r = false"
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@expect = [LoadConstant,SlotToReg, RegToSlot]
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@input = "r = false;return"
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@expect = [LoadConstant,SlotToReg, RegToSlot,LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -6,8 +6,8 @@ module Risc
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def setup
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super
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@input = "r = 5"
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@expect = [LoadConstant,SlotToReg, RegToSlot]
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@input = "r = 5;return"
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@expect = [LoadConstant,SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -6,9 +6,9 @@ module Risc
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def setup
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super
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@input = "@ivar = 5 ; r = @ivar"
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@input = "@ivar = 5 ; r = @ivar;return"
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@expect = [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg ,
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RegToSlot]
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RegToSlot, LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -6,11 +6,12 @@ module Risc
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def setup
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super
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@input = "r = 5.div4"
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@input = "r = 5.div4;return"
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@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
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FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot]
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FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot,
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LoadConstant, RegToSlot, Branch]
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end
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def test_local_assign_instructions
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assert_nil msg = check_nil , msg
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@ -7,12 +7,12 @@ module Risc
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def setup
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super
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@input = as_block("return 5")
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@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #4
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@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #4
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RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, #9
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RegToSlot, RegToSlot, RegToSlot, RegToSlot, SlotToReg, #14
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, #19
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, #24
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SlotToReg, FunctionCall, Label]
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SlotToReg, FunctionCall, Label] #29
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end
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def test_send_instructions
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@ -18,7 +18,7 @@ module Risc
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SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #44
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RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #49
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LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #54
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SlotToReg, DynamicJump, Label]
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SlotToReg, DynamicJump, Label, SlotToReg, RegToSlot, Branch]
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end
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def test_send_instructions
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@ -10,7 +10,7 @@ module Risc
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@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
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FunctionCall, Label]
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FunctionCall, Label, SlotToReg, RegToSlot, Branch]
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end
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def test_send_instructions
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@ -11,7 +11,7 @@ module Risc
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RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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LoadConstant, SlotToReg, RegToSlot, SlotToReg, FunctionCall,
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Label]
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Label, SlotToReg, RegToSlot, Branch]
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end
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def test_send_instructions
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@ -6,11 +6,11 @@ module Risc
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def setup
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super
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@input = "5.div4"
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@input = "return 5.div4"
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@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
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FunctionCall, Label]
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FunctionCall, Label, SlotToReg, RegToSlot, Branch]
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@produced = produce_body
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end
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@ -51,7 +51,7 @@ module Risc
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assert_reg_to_slot( sl , :r1 , :r3 , 7 )
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end
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def test_label
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sl = @produced.next( 17 )
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sl = @produced.next( 20 )
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assert_equal Risc::Label , sl.class
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assert_equal "return_label" , sl.name
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end
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@ -6,11 +6,12 @@ module Risc
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def setup
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super
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end;return"
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero,
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LoadConstant, OperatorInstruction, IsZero, Label, LoadConstant,
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SlotToReg, RegToSlot, Branch, Label, LoadConstant,
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SlotToReg, RegToSlot, Label]
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SlotToReg, RegToSlot, Label, LoadConstant, #34
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RegToSlot, Branch]
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end
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def test_if_instructions
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@ -6,10 +6,11 @@ module Risc
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def setup
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super
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@input = "if(@a) ; arg = 5 ; end"
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@input = "if(@a) ; arg = 5 ; end;return"
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero,
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LoadConstant, OperatorInstruction, IsZero, Label, LoadConstant,
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SlotToReg, RegToSlot, Label]
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SlotToReg, RegToSlot, Label, LoadConstant, #34
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RegToSlot, Branch]
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end
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def test_if_instructions
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@ -6,10 +6,11 @@ module Risc
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def setup
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super
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@input = "unless(@a) ; arg = 5 ; end"
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@input = "unless(@a) ; arg = 5 ; end;return"
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero, #4
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LoadConstant, OperatorInstruction, IsZero, Label, Branch, #9
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Label, LoadConstant, SlotToReg, RegToSlot, Label] #14
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Label, LoadConstant, SlotToReg, RegToSlot, Label, LoadConstant, #34
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RegToSlot, Branch] #14
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end
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def test_if_instructions
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@ -14,7 +14,7 @@ module Mom
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assert_nil Instruction.new("Hi").next
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end
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def test_raise
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assert_raises {Instruction.new(5)}
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assert_raises {Instruction.new(5)}
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end
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end
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end
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@ -7,7 +7,7 @@ module Mom
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def setup
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end
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def in_test_vool(body = "@ivar = 5")
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def in_test_vool(body = "@ivar = 5;return")
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code = in_Test("def meth; #{body};end")
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RubyX::RubyXCompiler.new(RubyX.default_test_options).ruby_to_mom(code)
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end
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@ -30,7 +30,7 @@ module Mom
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def test_compiles_all_risc
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compiler = in_test_vool().compilers.first.to_risc
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assert_equal Risc::LoadConstant , compiler.risc_instructions.next.class
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assert_equal 17 , compiler.risc_instructions.length
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assert_equal 20 , compiler.risc_instructions.length
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end
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end
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end
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@ -6,11 +6,11 @@ module Risc
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def setup
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super
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@input = "5.div4"
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@input = "return 5.div4"
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@expect = "something"
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end
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def instruction(num) # 18 is the main, see length in test/mom/send/test_setup_simple.rb
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produce_main.next( 18 + num)
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def instruction(num) # 21 is the main, see length in test/mom/send/test_setup_simple.rb
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produce_main.next( 21 + num)
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end
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def test_postamble_classes
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postamble.each_with_index do |ins , index|
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@ -6,14 +6,15 @@ module Risc
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def setup
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super
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@input = "while(5 > 0) ; @a = true; end"
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@input = "while(5 > 0) ; @a = true; end;return"
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@expect = [Label, LoadConstant, LoadConstant, SlotToReg, SlotToReg, #4
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RegToSlot, RegToSlot, RegToSlot, RegToSlot, LoadConstant, #9
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, SlotToReg, #14
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #19
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FunctionCall, Label, SlotToReg, LoadConstant, OperatorInstruction, #24
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IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, #29
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SlotToReg, RegToSlot, Branch, Label] #34
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SlotToReg, RegToSlot, Branch, Label, LoadConstant, #34
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RegToSlot, Branch] #34
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end
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def test_while_instructions
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@ -6,10 +6,11 @@ module Risc
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def setup
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super
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@input = "while(@a) ; arg = 5 end"
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction,
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IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant,
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SlotToReg, RegToSlot, Branch, Label]
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@input = "while(@a) ; arg = 5 end;return"
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, #4
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IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, #9
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SlotToReg, RegToSlot, Branch, Label, LoadConstant, #14
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RegToSlot, Branch] #19
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end
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def test_while_instructions
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