Fixing tests for implicit return

previous commit affected rather many test, as the implicit returns add extra instructions
Also added some explicit returns, so as not to test the return logic too much. return (ie return nl) is a knonwn 3 risc operation.
This commit is contained in:
2019-08-17 23:29:42 +03:00
parent 32f908c127
commit 5a43cbff15
43 changed files with 152 additions and 107 deletions

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@ -6,8 +6,8 @@ module Risc
def setup
super
@input = "arg = 5"
@expect = [LoadConstant, SlotToReg, RegToSlot]
@input = "arg = 5;return"
@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -6,8 +6,8 @@ module Risc
def setup
super
@input = "@ivar = 5"
@expect = [LoadConstant, SlotToReg, RegToSlot]
@input = "@ivar = 5;return"
@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions

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@ -6,8 +6,9 @@ module Risc
def setup
super
@input = "local = arg"
@expect = [SlotToReg, SlotToReg, SlotToReg, RegToSlot]
@input = "local = arg; return local"
@expect = [SlotToReg, SlotToReg, SlotToReg, RegToSlot, SlotToReg, #4
SlotToReg, RegToSlot, Branch] #9
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -6,8 +6,8 @@ module Risc
def setup
super
@input = "r = false"
@expect = [LoadConstant,SlotToReg, RegToSlot]
@input = "r = false;return"
@expect = [LoadConstant,SlotToReg, RegToSlot,LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -6,8 +6,8 @@ module Risc
def setup
super
@input = "r = 5"
@expect = [LoadConstant,SlotToReg, RegToSlot]
@input = "r = 5;return"
@expect = [LoadConstant,SlotToReg, RegToSlot, LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -6,9 +6,9 @@ module Risc
def setup
super
@input = "@ivar = 5 ; r = @ivar"
@input = "@ivar = 5 ; r = @ivar;return"
@expect = [LoadConstant, SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg ,
RegToSlot]
RegToSlot, LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -6,11 +6,12 @@ module Risc
def setup
super
@input = "r = 5.div4"
@input = "r = 5.div4;return"
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot]
FunctionCall, Label, SlotToReg, SlotToReg, RegToSlot,
LoadConstant, RegToSlot, Branch]
end
def test_local_assign_instructions
assert_nil msg = check_nil , msg

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@ -7,12 +7,12 @@ module Risc
def setup
super
@input = as_block("return 5")
@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #4
@expect = [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #4
RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, #9
RegToSlot, RegToSlot, RegToSlot, RegToSlot, SlotToReg, #14
SlotToReg, RegToSlot, SlotToReg, SlotToReg, SlotToReg, #19
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, #24
SlotToReg, FunctionCall, Label]
SlotToReg, FunctionCall, Label] #29
end
def test_send_instructions

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@ -18,7 +18,7 @@ module Risc
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #44
RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #49
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #54
SlotToReg, DynamicJump, Label]
SlotToReg, DynamicJump, Label, SlotToReg, RegToSlot, Branch]
end
def test_send_instructions

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@ -10,7 +10,7 @@ module Risc
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label]
FunctionCall, Label, SlotToReg, RegToSlot, Branch]
end
def test_send_instructions

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@ -11,7 +11,7 @@ module Risc
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, RegToSlot, SlotToReg, FunctionCall,
Label]
Label, SlotToReg, RegToSlot, Branch]
end
def test_send_instructions

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@ -6,11 +6,11 @@ module Risc
def setup
super
@input = "5.div4"
@input = "return 5.div4"
@expect = [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg,
FunctionCall, Label]
FunctionCall, Label, SlotToReg, RegToSlot, Branch]
@produced = produce_body
end
@ -51,7 +51,7 @@ module Risc
assert_reg_to_slot( sl , :r1 , :r3 , 7 )
end
def test_label
sl = @produced.next( 17 )
sl = @produced.next( 20 )
assert_equal Risc::Label , sl.class
assert_equal "return_label" , sl.name
end

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@ -6,11 +6,12 @@ module Risc
def setup
super
@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
@input = "if(@a) ; arg = 5 ; else; arg = 6; end;return"
@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero,
LoadConstant, OperatorInstruction, IsZero, Label, LoadConstant,
SlotToReg, RegToSlot, Branch, Label, LoadConstant,
SlotToReg, RegToSlot, Label]
SlotToReg, RegToSlot, Label, LoadConstant, #34
RegToSlot, Branch]
end
def test_if_instructions

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@ -6,10 +6,11 @@ module Risc
def setup
super
@input = "if(@a) ; arg = 5 ; end"
@input = "if(@a) ; arg = 5 ; end;return"
@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero,
LoadConstant, OperatorInstruction, IsZero, Label, LoadConstant,
SlotToReg, RegToSlot, Label]
SlotToReg, RegToSlot, Label, LoadConstant, #34
RegToSlot, Branch]
end
def test_if_instructions

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@ -6,10 +6,11 @@ module Risc
def setup
super
@input = "unless(@a) ; arg = 5 ; end"
@input = "unless(@a) ; arg = 5 ; end;return"
@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsZero, #4
LoadConstant, OperatorInstruction, IsZero, Label, Branch, #9
Label, LoadConstant, SlotToReg, RegToSlot, Label] #14
Label, LoadConstant, SlotToReg, RegToSlot, Label, LoadConstant, #34
RegToSlot, Branch] #14
end
def test_if_instructions

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@ -14,7 +14,7 @@ module Mom
assert_nil Instruction.new("Hi").next
end
def test_raise
assert_raises {Instruction.new(5)}
assert_raises {Instruction.new(5)}
end
end
end

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@ -7,7 +7,7 @@ module Mom
def setup
end
def in_test_vool(body = "@ivar = 5")
def in_test_vool(body = "@ivar = 5;return")
code = in_Test("def meth; #{body};end")
RubyX::RubyXCompiler.new(RubyX.default_test_options).ruby_to_mom(code)
end
@ -30,7 +30,7 @@ module Mom
def test_compiles_all_risc
compiler = in_test_vool().compilers.first.to_risc
assert_equal Risc::LoadConstant , compiler.risc_instructions.next.class
assert_equal 17 , compiler.risc_instructions.length
assert_equal 20 , compiler.risc_instructions.length
end
end
end

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@ -6,11 +6,11 @@ module Risc
def setup
super
@input = "5.div4"
@input = "return 5.div4"
@expect = "something"
end
def instruction(num) # 18 is the main, see length in test/mom/send/test_setup_simple.rb
produce_main.next( 18 + num)
def instruction(num) # 21 is the main, see length in test/mom/send/test_setup_simple.rb
produce_main.next( 21 + num)
end
def test_postamble_classes
postamble.each_with_index do |ins , index|

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@ -6,14 +6,15 @@ module Risc
def setup
super
@input = "while(5 > 0) ; @a = true; end"
@input = "while(5 > 0) ; @a = true; end;return"
@expect = [Label, LoadConstant, LoadConstant, SlotToReg, SlotToReg, #4
RegToSlot, RegToSlot, RegToSlot, RegToSlot, LoadConstant, #9
SlotToReg, RegToSlot, LoadConstant, SlotToReg, SlotToReg, #14
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, #19
FunctionCall, Label, SlotToReg, LoadConstant, OperatorInstruction, #24
IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, #29
SlotToReg, RegToSlot, Branch, Label] #34
SlotToReg, RegToSlot, Branch, Label, LoadConstant, #34
RegToSlot, Branch] #34
end
def test_while_instructions

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@ -6,10 +6,11 @@ module Risc
def setup
super
@input = "while(@a) ; arg = 5 end"
@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction,
IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant,
SlotToReg, RegToSlot, Branch, Label]
@input = "while(@a) ; arg = 5 end;return"
@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, #4
IsZero, LoadConstant, OperatorInstruction, IsZero, LoadConstant, #9
SlotToReg, RegToSlot, Branch, Label, LoadConstant, #14
RegToSlot, Branch] #19
end
def test_while_instructions