more headway on the (new) frame implementation
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@ -69,7 +69,7 @@ module Arm
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operand = reg_code(right)
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immediate = 0 # ie not immediate is register
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else
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raise "invalid operand argument #{right.inspect} , #{inspect}"
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raise "invalid operand argument #{right.class} , #{self.class}"
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end
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op = shift_handling
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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@ -86,7 +86,7 @@ module Arm
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# by now we have the extra add so assemble that
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if(@extra)
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@extra.assemble(io)
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puts "Assemble extra at #{self.position.to_s(16)}"
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#puts "Assemble extra at #{self.position.to_s(16)}"
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end
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end
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def shift val , by
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