rewrite new_int with builder
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86462e238a
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@ -50,12 +50,12 @@ module Risc
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# infer the type from a symbol. In the simplest case the sybbol is the class name
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# infer the type from a symbol. In the simplest case the sybbol is the class name
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# But in building sometimes variations are needed, so next_message or caller work
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# But in building sometimes variations are needed, so next_message or caller work
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# too (and return Message)
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# too (and return Message)
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# A general "_reg" or "_obj" at the end of the name will be removed
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# A general "_reg"/"_obj" or "_tmp" at the end of the name will be removed
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# An error is raised if the symbol/object can not be inferred
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# An error is raised if the symbol/object can not be inferred
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def infer_type( name )
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def infer_type( name )
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as_string = name.to_s
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as_string = name.to_s
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parts = as_string.split("_")
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parts = as_string.split("_")
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if(parts.last == "reg" or parts.last == "obj")
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if(parts.last == "reg" or parts.last == "obj" or parts.last == "tmp")
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parts.pop
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parts.pop
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as_string = parts.join("_")
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as_string = parts.join("_")
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end
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end
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@ -97,6 +97,7 @@ module Risc
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@names[left] = r
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@names[left] = r
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@names[right] = l
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@names[right] = l
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end
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end
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# build code using dsl (see __init__ or MessageSetup for examples)
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# build code using dsl (see __init__ or MessageSetup for examples)
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# names (that ruby would resolve to a variable/method) are converted
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# names (that ruby would resolve to a variable/method) are converted
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# to registers. << means assignment and [] is supported both on
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# to registers. << means assignment and [] is supported both on
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@ -123,23 +124,15 @@ module Risc
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# move a machine int from register "from" to a Parfait::Integer in register "to"
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# move a machine int from register "from" to a Parfait::Integer in register "to"
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# have to grab an integer from space and stick it in the "to" register first.
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# have to grab an integer from space and stick it in the "to" register first.
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def add_new_int( source , from, to )
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def add_new_int( source , from, to )
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source += "add_new_int "
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to.builder = self # esecially div10 comes in without having used builder
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space = compiler.use_reg(:Space)
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from.builder = self # not named regs, different regs ==> silent errors
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int = compiler.use_reg(:Integer)
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build do
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space_i = space.resolve_index(:next_integer)
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space << Parfait.object_space
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add_load_constant( source + "space" , Parfait.object_space , space )
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to << space[:next_integer]
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add_slot_to_reg( source + "next_i1" , space , space_i , to)
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integer_tmp << to[:next_integer]
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add_slot_to_reg( source + "next_i2" , to , int.resolve_index(:next_integer) , int)
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space[:next_integer] << integer_tmp
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add_reg_to_slot( source + "store link" , int , space , space_i )
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to[Parfait::Integer.integer_index] << from
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add_reg_to_slot( source + "store value" , from , to , Parfait::Integer.integer_index)
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end
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# build do
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# space << Parfait.object_space
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# to << space[:next_integer]
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# integer << to[:next_integer]
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# space[:next_integer] << integer
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# to[Parfait::Integer.integer_index] << from
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# end
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end
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end
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# for computationally building code (ie writing assembler) these short cuts
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# for computationally building code (ie writing assembler) these short cuts
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@ -34,6 +34,14 @@ module Risc
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assert_equal 2 , get_return
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assert_equal 2 , get_return
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end
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end
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def test_load_space
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load_ins = main_ticks 55
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assert_load load_ins, Parfait::Space
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end
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def test_load_to
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to = main_ticks 56
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assert_slot_to_reg to , :r5 , 5 ,:r2
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end
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def test_load_25
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def test_load_25
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load_ins = main_ticks 9
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load_ins = main_ticks 9
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assert_equal LoadConstant , load_ins.class
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assert_equal LoadConstant , load_ins.class
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@ -12,35 +12,35 @@ module Risc
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def test_chain
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def test_chain
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#show_main_ticks # get output of what is
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#show_main_ticks # get output of what is
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check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero,
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SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero, # 10
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SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant,
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SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant,
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RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg,
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RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, # 20
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 30
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 40
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 50
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 60
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 70
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, RegToSlot, Branch, LoadConstant,
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OperatorInstruction, IsZero, RegToSlot, Branch, LoadConstant, # 80
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SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 90
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SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg,
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SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg,
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RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump,
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RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump, # 100
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SlotToReg, SlotToReg, LoadData, OperatorInstruction, LoadConstant,
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SlotToReg, SlotToReg, LoadData, OperatorInstruction, LoadConstant,
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SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot,
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SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, # 110
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SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant,
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SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant,
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SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 120
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SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, SlotToReg, RegToSlot, Branch, Branch,
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SlotToReg, SlotToReg, RegToSlot, Branch, Branch, # 130
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SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
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RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, # 140
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FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall,
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FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall,
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NilClass]
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NilClass, ]
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assert_equal Fixnum , get_return.class
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assert_equal Fixnum , get_return.class
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assert_equal 1 , get_return
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assert_equal 1 , get_return
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end
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end
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@ -25,6 +25,9 @@ module Risc
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def test_caller_reg
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def test_caller_reg
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assert_equal :Message , @builder.infer_type(:caller_reg).class_name
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assert_equal :Message , @builder.infer_type(:caller_reg).class_name
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end
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end
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def test_caller_tmp
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assert_equal :Message , @builder.infer_type(:caller_tmp).class_name
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end
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def test_caller_obj
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def test_caller_obj
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assert_equal :Message , @builder.infer_type(:caller_obj).class_name
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assert_equal :Message , @builder.infer_type(:caller_obj).class_name
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end
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end
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