rewrite new_int with builder

This commit is contained in:
Torsten Ruger 2018-08-13 18:02:34 +03:00
parent 86462e238a
commit 55bc9c5273
4 changed files with 52 additions and 48 deletions

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@ -50,12 +50,12 @@ module Risc
# infer the type from a symbol. In the simplest case the sybbol is the class name # infer the type from a symbol. In the simplest case the sybbol is the class name
# But in building sometimes variations are needed, so next_message or caller work # But in building sometimes variations are needed, so next_message or caller work
# too (and return Message) # too (and return Message)
# A general "_reg" or "_obj" at the end of the name will be removed # A general "_reg"/"_obj" or "_tmp" at the end of the name will be removed
# An error is raised if the symbol/object can not be inferred # An error is raised if the symbol/object can not be inferred
def infer_type( name ) def infer_type( name )
as_string = name.to_s as_string = name.to_s
parts = as_string.split("_") parts = as_string.split("_")
if(parts.last == "reg" or parts.last == "obj") if(parts.last == "reg" or parts.last == "obj" or parts.last == "tmp")
parts.pop parts.pop
as_string = parts.join("_") as_string = parts.join("_")
end end
@ -97,6 +97,7 @@ module Risc
@names[left] = r @names[left] = r
@names[right] = l @names[right] = l
end end
# build code using dsl (see __init__ or MessageSetup for examples) # build code using dsl (see __init__ or MessageSetup for examples)
# names (that ruby would resolve to a variable/method) are converted # names (that ruby would resolve to a variable/method) are converted
# to registers. << means assignment and [] is supported both on # to registers. << means assignment and [] is supported both on
@ -123,23 +124,15 @@ module Risc
# move a machine int from register "from" to a Parfait::Integer in register "to" # move a machine int from register "from" to a Parfait::Integer in register "to"
# have to grab an integer from space and stick it in the "to" register first. # have to grab an integer from space and stick it in the "to" register first.
def add_new_int( source , from, to ) def add_new_int( source , from, to )
source += "add_new_int " to.builder = self # esecially div10 comes in without having used builder
space = compiler.use_reg(:Space) from.builder = self # not named regs, different regs ==> silent errors
int = compiler.use_reg(:Integer) build do
space_i = space.resolve_index(:next_integer) space << Parfait.object_space
add_load_constant( source + "space" , Parfait.object_space , space ) to << space[:next_integer]
add_slot_to_reg( source + "next_i1" , space , space_i , to) integer_tmp << to[:next_integer]
add_slot_to_reg( source + "next_i2" , to , int.resolve_index(:next_integer) , int) space[:next_integer] << integer_tmp
add_reg_to_slot( source + "store link" , int , space , space_i ) to[Parfait::Integer.integer_index] << from
add_reg_to_slot( source + "store value" , from , to , Parfait::Integer.integer_index) end
# build do
# space << Parfait.object_space
# to << space[:next_integer]
# integer << to[:next_integer]
# space[:next_integer] << integer
# to[Parfait::Integer.integer_index] << from
# end
end end
# for computationally building code (ie writing assembler) these short cuts # for computationally building code (ie writing assembler) these short cuts

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@ -34,6 +34,14 @@ module Risc
assert_equal 2 , get_return assert_equal 2 , get_return
end end
def test_load_space
load_ins = main_ticks 55
assert_load load_ins, Parfait::Space
end
def test_load_to
to = main_ticks 56
assert_slot_to_reg to , :r5 , 5 ,:r2
end
def test_load_25 def test_load_25
load_ins = main_ticks 9 load_ins = main_ticks 9
assert_equal LoadConstant , load_ins.class assert_equal LoadConstant , load_ins.class

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@ -12,35 +12,35 @@ module Risc
def test_chain def test_chain
#show_main_ticks # get output of what is #show_main_ticks # get output of what is
check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, check_main_chain [LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero, # 10
SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant, SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant,
RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, # 20
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, Branch, SlotToReg, Branch, OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 30
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, Branch, SlotToReg, Branch, OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 40
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, Branch, SlotToReg, Branch, OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 50
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, Branch, SlotToReg, Branch, OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 60
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, Branch, SlotToReg, Branch, OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 70
LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg, LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
OperatorInstruction, IsZero, RegToSlot, Branch, LoadConstant, OperatorInstruction, IsZero, RegToSlot, Branch, LoadConstant, # 80
SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot, SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 90
SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg,
RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump, RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump, # 100
SlotToReg, SlotToReg, LoadData, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, LoadData, OperatorInstruction, LoadConstant,
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, # 110
SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant,
SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 120
SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, RegToSlot, Branch, Branch, SlotToReg, SlotToReg, RegToSlot, Branch, Branch, # 130
SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg, SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, # 140
FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall, FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall,
NilClass] NilClass, ]
assert_equal Fixnum , get_return.class assert_equal Fixnum , get_return.class
assert_equal 1 , get_return assert_equal 1 , get_return
end end

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@ -25,6 +25,9 @@ module Risc
def test_caller_reg def test_caller_reg
assert_equal :Message , @builder.infer_type(:caller_reg).class_name assert_equal :Message , @builder.infer_type(:caller_reg).class_name
end end
def test_caller_tmp
assert_equal :Message , @builder.infer_type(:caller_tmp).class_name
end
def test_caller_obj def test_caller_obj
assert_equal :Message , @builder.infer_type(:caller_obj).class_name assert_equal :Message , @builder.infer_type(:caller_obj).class_name
end end