diff --git a/lib/arm/memory_instruction.rb b/lib/arm/memory_instruction.rb
index bc06f126..6185e40f 100644
--- a/lib/arm/memory_instruction.rb
+++ b/lib/arm/memory_instruction.rb
@@ -25,7 +25,7 @@ module Arm
       arg = @left
       arg = arg.symbol if( arg.is_a? ::Register::RegisterReference )
       #str / ldr are _serious instructions. With BIG possibilities not half are implemented
-      if (arg.is_a?(Symbol)) #symbol is register
+      if (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterReference)) #symbol is register
         rn = arg
         if @right
           operand = @right
@@ -73,7 +73,7 @@ module Arm
       w = 0 #W flag
       byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
       instuction_class =  0b01 # OPC_MEMORY_ACCESS
-      if operand.is_a?(Symbol)
+      if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference))
         val = reg_code(operand) 
         @pre_post_index = 0
         i = 1  # not quite sure about this, but it gives the output of as. read read read.
diff --git a/lib/arm/move_instruction.rb b/lib/arm/move_instruction.rb
index 637cbe8d..edd2b9fe 100644
--- a/lib/arm/move_instruction.rb
+++ b/lib/arm/move_instruction.rb
@@ -65,7 +65,7 @@ module Arm
           raise "only simple 2 byte implemented #{self.inspect}" if operand > 255
           @extra = ::Register::RegisterMachine.instance.add( to , to , (right.integer && 0xFF) ,  shift_lsr: 8)
         end
-      elsif (right.is_a?(Symbol))
+      elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
         operand = reg_code(right)    
         immediate = 0                # ie not immediate is register
       else