fixing most of the risc tests

This commit is contained in:
2019-08-23 15:31:22 +03:00
parent 50c172915e
commit 4ca16e5f9a
21 changed files with 265 additions and 293 deletions

View File

@ -11,48 +11,44 @@ module Risc
def test_chain
#show_main_ticks # get output of what is
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, SlotToReg, FunctionCall, LoadConstant, # 20
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg,
RegToSlot, SlotToReg, SlotToReg, SlotToReg, SlotToReg, # 30
Branch, OperatorInstruction, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, # 40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg, # 50
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
Branch, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, # 60
Transfer, SlotToReg, SlotToReg, Syscall, NilClass, ]
check_main_chain [LoadConstant, RegToSlot, LoadConstant, SlotToReg, RegToSlot, #5
LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg, #10
RegToSlot, SlotToReg, FunctionCall, LoadConstant, SlotToReg, #15
LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, RegToSlot, #20
SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, #25
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, #30
Branch, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, #35
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg, #40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, #45
Transfer, SlotToReg, SlotToReg, Syscall, NilClass,] #50
assert_equal 10 , get_return
end
def base_ticks(num)
main_ticks(21 + num)
main_ticks(13 + num)
end
def test_load_5
lod = main_ticks( 12 )
assert_load( lod , Parfait::Integer , :r1)
assert_equal 5 , lod.constant.value
def test_base
cal = main_ticks( 13 )
assert_equal FunctionCall , cal.class
end
def test_load_receiver
sl = base_ticks( 6 )
sl = base_ticks( 8 )
assert_slot_to_reg( sl , :r0 , 2 , :r2)
end
def test_reduce_receiver
sl = base_ticks( 7 )
sl = base_ticks( 9 )
assert_slot_to_reg( sl , :r2 , 2 , :r2)
end
def test_slot_args #load args from message
sl = base_ticks( 8 )
sl = base_ticks( 10 )
assert_slot_to_reg( sl , :r0 , 9 , :r3)
end
def test_reduce_arg
sl = base_ticks( 9 )
sl = base_ticks( 11 )
assert_slot_to_reg( sl , :r3 , 2 , :r3)
assert_equal 5 , @interpreter.get_register(:r3)
end
def test_op
op = base_ticks(11)
op = base_ticks(12)
assert_equal OperatorInstruction , op.class
assert_equal :+ , op.operator
assert_equal :r2 , op.left.symbol
@ -61,19 +57,19 @@ module Risc
assert_equal 5 , @interpreter.get_register(:r3)
end
def test_move_res_to_int
int = base_ticks( 12 )
int = base_ticks( 13 )
assert_reg_to_slot( int , :r2 , :r1 , 2)
end
def test_move_int_to_reg
int = base_ticks( 13 )
int = base_ticks( 14 )
assert_reg_to_slot( int , :r1 , :r0 , 5)
end
def test_move_fix_to_result
sl = base_ticks( 14 )
sl = base_ticks( 15 )
assert_slot_to_reg( sl , :r0 , 5 , :r1)
end
def test_start_return_sequence
sl = base_ticks( 15 )
sl = base_ticks( 16 )
assert_slot_to_reg( sl , :r0 , 6 , :r2)
end
end