diff --git a/lib/phisol/compiler.rb b/lib/phisol/compiler.rb
index 743be14c..341f64a0 100644
--- a/lib/phisol/compiler.rb
+++ b/lib/phisol/compiler.rb
@@ -2,6 +2,7 @@ module Phisol
   class Compiler < AST::Processor
 
     def initialize()
+      @regs = []
     end
     def handler_missing node
       raise "No handler  on_#{node.type}(node)"
@@ -27,6 +28,21 @@ module Phisol
       compiler.process statement
     end
 
+    # require a (temporary) register. code must give this back with release_reg
+    def use_reg
+      if @regs.empty?
+        reg = Register.tmp_reg
+      else
+        reg = @regs.last.next_reg_use
+      end
+      @regs << reg
+      return reg
+    end
+
+    def release_reg reg
+      last = @regs.pop
+      raise "released register in wrong order, expect #{last} but was #{reg}" if reg != last
+    end
   end
 end
 
diff --git a/lib/phisol/compiler/operator_value.rb b/lib/phisol/compiler/operator_value.rb
index 5e20aab7..04493b95 100644
--- a/lib/phisol/compiler/operator_value.rb
+++ b/lib/phisol/compiler/operator_value.rb
@@ -8,8 +8,8 @@ module Phisol
       right_slot = process(right_e)
       puts "left #{left_slot}"
       puts "right #{right_slot}"
-      tmp1 = Register.tmp_reg
-      tmp2 = tmp1.next_reg_use
+      tmp1 = use_reg
+      tmp2 = use_reg
       get = Register.get_slot_to(statement , left_slot , tmp1 )
       get2 = Register.get_slot_to(statement , right_slot , tmp2 )
       puts "GET #{get}"
@@ -18,7 +18,8 @@ module Phisol
       @method.source.add_code get2
 
       @method.source.add_code Register::OperatorInstruction.new(statement,operator, tmp1,tmp2)
-
+      release_reg tmp2
+      release_reg tmp1
       Virtual::Return.new(:int )
     end