codong RegisterSlot with reg and slot
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@ -5,7 +5,7 @@ module Risc
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# Both use a base memory (a register)
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# Both use a base memory (a register)
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# This is because that is what cpu's can do. In programming terms this would be accessing
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# This is because that is what cpu's can do. In programming terms this would be accessing
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# an element in an array, in the case of RegToSlot setting the register in the array.
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# an element in an array, in the case of RegToSlot setting the register in the array.
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# btw: to move data between registers, use Transfer
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# btw: to move data between registers, use Transfer
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@ -16,6 +16,8 @@ module Risc
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# Produce a RegToSlot instruction.
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# Produce a RegToSlot instruction.
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# From and to are registers
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# From and to are registers
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# index may be a Symbol in which case is resolves with resolve_index.
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# index may be a Symbol in which case is resolves with resolve_index.
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#
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# The slot is ultimately a memory location, so no new register is created
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def self.reg_to_slot( source , from , to , index )
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def self.reg_to_slot( source , from , to , index )
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raise "Not register #{to}" unless RegisterValue.look_like_reg(to)
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raise "Not register #{to}" unless RegisterValue.look_like_reg(to)
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index = to.resolve_index(index) if index.is_a?(Symbol)
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index = to.resolve_index(index) if index.is_a?(Symbol)
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@ -14,8 +14,9 @@ module Risc
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end
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end
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# Produce a SlotToReg instruction.
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# Produce a SlotToReg instruction.
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# Array and to are registers
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# Array is a register
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# index may be a Symbol in which case is resolves with resolve_index.
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# index may be a Symbol in which case is resolves with resolve_index.
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# a new regsister will be created as the result, ie the reg part for slot_to_reg
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def self.slot_to_reg( source , array , index )
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def self.slot_to_reg( source , array , index )
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raise "Register #{array}" if RegisterValue.look_like_reg(array.symbol)
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raise "Register #{array}" if RegisterValue.look_like_reg(array.symbol)
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index = array.resolve_index(index) if index.is_a?(Symbol)
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index = array.resolve_index(index) if index.is_a?(Symbol)
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@ -23,10 +23,36 @@ module Risc
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# fullfil the objects purpose by creating a RegToSlot instruction from
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# fullfil the objects purpose by creating a RegToSlot instruction from
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# itself (the slot) and the register given
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# itself (the slot) and the register given
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def <<( reg )
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def <<( reg )
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raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
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case reg
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reg_to_slot = Risc.reg_to_slot("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
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when RegisterValue
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puts reg.symbol
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to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
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when RegisterSlot
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puts reg.register.symbol
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reg = to_reg("reduce #{@register.symbol}[@index]")
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to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
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else
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raise "not reg value or slot #{reg}"
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end
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end
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# push the given register into the slot that self represents
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# ie create a slot_to_reg instruction and add to the compiler
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# the register represents and "array", and the content of the
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# given register from, is pushed to the memory at register[index]
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def to_mem(source , from )
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reg_to_slot = Risc.reg_to_slot(source , from , register, index)
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compiler.add_code(reg_to_slot) if compiler
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compiler.add_code(reg_to_slot) if compiler
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reg_to_slot
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reg_to_slot.register
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end
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# load the conntent of the slot that self descibes into a a new register.
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# the regsiter is created, and the slot_to_reg instruction added to the
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# compiler. the return is a bit like @register[@index]
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def to_reg(source )
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slot_to_reg = Risc.slot_to_reg(source , register, index)
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compiler.add_code(slot_to_reg) if compiler
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slot_to_reg.register
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end
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end
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# similar to above (<< which produces reg_to_slot), this produces reg_to_byte
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# similar to above (<< which produces reg_to_slot), this produces reg_to_byte
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@ -144,6 +144,7 @@ module Risc
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when RegisterValue
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when RegisterValue
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ins = Risc.transfer("#{right.type} to #{self.type}" , right , self)
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ins = Risc.transfer("#{right.type} to #{self.type}" , right , self)
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when RegisterSlot
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when RegisterSlot
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raise "logic error, after creating the reg, need to transfer"
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ins = Risc::SlotToReg.new("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
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ins = Risc::SlotToReg.new("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
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else
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else
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raise "not implemented for #{right.class}:#{right}"
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raise "not implemented for #{right.class}:#{right}"
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@ -1,71 +1,53 @@
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require_relative "../helper"
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require_relative "../helper"
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module Risc
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module Risc
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class TestRegisterSlot < MiniTest::Test
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class TestRegisterSlot1 < MiniTest::Test
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def setup
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def setup
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Parfait.boot!(Parfait.default_test_options)
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Parfait.boot!(Parfait.default_test_options)
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@r0 = RegisterValue.new(:message , :Message)
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@compiler = Risc.test_compiler
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@r1 = RegisterValue.new(:id_1234 , :Space)
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@r0 = RegisterValue.new(:message , :Message).set_compiler(@compiler)
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@r2 = RegisterValue.new(:id_1256 , :Factory)
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end
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end
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def test_class_name_type
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def test_reg_to_slot_reg
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assert_equal :Message , @r0.class_name
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reg = @r0[:next_message] << @r0
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assert_equal RegisterValue , reg.class
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assert_equal :message , reg.symbol
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assert_equal "Message_Type" , reg.type.name
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end
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end
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def test_class_name_fix
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def test_reg_to_slot_inst
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assert_equal :Integer , RegisterValue.new(:id_234 , :Integer).class_name
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@r0[:next_message] << @r0
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assert_equal RegToSlot , @compiler.current.class
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assert_equal @r0 , @compiler.current.register
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assert_equal 1 , @compiler.current.index
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assert_equal :message , @compiler.current.array.symbol
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end
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end
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def test_r0
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end
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assert_equal :message , @r0.symbol
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class TestRegisterSlot2 < MiniTest::Test
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def setup
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Parfait.boot!(Parfait.default_test_options)
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@compiler = Risc.test_compiler
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@r0 = RegisterValue.new(:message , :Message).set_compiler(@compiler)
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end
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end
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def test_load_label
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def test_reg_to_slot_reg
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label = Risc::Label.new("HI","ho" , FakeAddress.new(0))
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reg = @r0[:next_message] << @r0[:next_message]
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move = @r1 << label
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assert_equal RegisterValue , reg.class
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assert_equal LoadConstant , move.class
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assert_equal :"message.message" , reg.symbol
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assert_equal "Message_Type" , reg.type.name
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end
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end
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def test_transfer
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def test_reg_to_slot_inst1
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transfer = @r0 << @r1
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@r0[:next_message] << @r0[:next_message]
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assert_equal Transfer , transfer.class
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inst = @compiler.risc_instructions.next
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assert_equal SlotToReg , inst.class
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assert_equal :"message.message" , inst.register.symbol
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assert_equal 1 , inst.index
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assert_equal :message , inst.array.symbol
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end
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end
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def test_index_op
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def test_reg_to_slot_inst2
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message = @r0[:next_message]
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@r0[:next_message] << @r0[:next_message]
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assert_equal RegisterSlot , message.class
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inst = @compiler.current
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assert_equal :next_message , message.index
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assert_equal RegToSlot , inst.class
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assert_equal @r0 , message.register
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assert_equal :"message.message" , inst.register.symbol
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end
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assert_equal 1 , inst.index
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def test_operator
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assert_equal :message , inst.array.symbol
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ret = @r0.op :<< , @r1
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assert_equal OperatorInstruction , ret.class
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assert_equal @r0 , ret.left
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assert_equal @r1 , ret.right
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assert_equal :<< , ret.operator
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end
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def test_byte_to_reg
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instr = @r0 <= @r1[1]
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assert_equal ByteToReg , instr.class
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assert_equal @r1 , instr.array
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assert_equal @r0 , instr.register
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assert_equal 1 , instr.index
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end
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def est_slot_to_reg
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instr = @r0 << @r2[:next_object]
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assert_equal SlotToReg , instr.class
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assert_equal @r0 , instr.register
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assert_equal 2 , instr.index
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assert_equal @r1 , instr.array
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end
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def test_reg_to_byte
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instr = @r1[1] <= @r0
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assert_equal RegToByte , instr.class
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assert_equal @r1 , instr.array
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assert_equal @r0 , instr.register
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assert_equal 1 , instr.index
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end
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def est_reg_to_slot
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instr = @r2[:next_object] << @r0
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assert_equal RegToSlot , instr.class
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assert_equal @r0 , instr.register
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assert_equal 2 , instr.index
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assert_equal @r1 , instr.array
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end
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end
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end
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end
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end
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end
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@ -78,12 +78,5 @@ module Risc
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assert_equal @r0 , instr.register
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assert_equal @r0 , instr.register
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assert_equal 1 , instr.index
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assert_equal 1 , instr.index
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end
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end
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def est_reg_to_slot
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instr = @r2[:next_object] << @r0
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assert_equal RegToSlot , instr.class
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assert_equal @r0 , instr.register
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assert_equal 2 , instr.index
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assert_equal @r1 , instr.array
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end
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end
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end
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end
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end
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