codong RegisterSlot with reg and slot

lib/risc/instructions/reg_to_slot.rb

@@ -5,7 +5,7 @@ module Risc
   # Both use a base memory (a register)
 
   # This is because that is what cpu's can do. In programming terms this would be accessing
-  #  an element in an array, in the case of RegToSlot setting the register in the array.
+  # an element in an array, in the case of RegToSlot setting the register in the array.
 
   # btw: to move data between registers, use Transfer
 
@@ -16,6 +16,8 @@ module Risc
   # Produce a RegToSlot instruction.
   # From and to are registers
   # index may be a Symbol in which case is resolves with resolve_index.
+  #
+  # The slot is ultimately a memory location, so no new register is created
   def self.reg_to_slot( source , from , to , index )
     raise "Not register #{to}" unless RegisterValue.look_like_reg(to)
     index = to.resolve_index(index) if index.is_a?(Symbol)

lib/risc/instructions/slot_to_reg.rb

@@ -14,8 +14,9 @@ module Risc
   end
 
   # Produce a SlotToReg instruction.
-  # Array and to are registers
+  # Array is a register
   # index may be a Symbol in which case is resolves with resolve_index.
+  # a new regsister will be created as the result, ie the reg part for slot_to_reg
   def self.slot_to_reg( source , array , index )
     raise "Register #{array}" if RegisterValue.look_like_reg(array.symbol)
     index = array.resolve_index(index) if index.is_a?(Symbol)

lib/risc/register_slot.rb

@@ -23,10 +23,36 @@ module Risc
     # fullfil the objects purpose by creating a RegToSlot instruction from
     # itself (the slot) and the register given
     def <<( reg )
-      raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
-      reg_to_slot = Risc.reg_to_slot("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
+      case reg
+      when RegisterValue
+        puts reg.symbol
+        to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
+      when RegisterSlot
+        puts reg.register.symbol
+        reg = to_reg("reduce #{@register.symbol}[@index]")
+        to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)        
+      else
+        raise "not reg value or slot #{reg}"
+      end
+    end
+
+    # push the given register into the slot that self represents
+    # ie create a slot_to_reg instruction and add to the compiler
+    # the register represents and "array", and the content of the
+    # given register from, is pushed to the memory at register[index]
+    def to_mem(source , from )
+      reg_to_slot = Risc.reg_to_slot(source , from , register, index)
       compiler.add_code(reg_to_slot) if compiler
-      reg_to_slot
+      reg_to_slot.register
+    end
+
+    # load the conntent of the slot that self descibes into a a new register.
+    # the regsiter is created, and the slot_to_reg instruction added to the
+    # compiler. the return is a bit like @register[@index]
+    def to_reg(source )
+      slot_to_reg = Risc.slot_to_reg(source , register, index)
+      compiler.add_code(slot_to_reg) if compiler
+      slot_to_reg.register
     end
 
     # similar to above (<< which produces reg_to_slot), this produces reg_to_byte

lib/risc/register_value.rb

@@ -144,6 +144,7 @@ module Risc
       when RegisterValue
         ins = Risc.transfer("#{right.type} to #{self.type}" , right , self)
       when RegisterSlot
+        raise "logic error, after creating the reg, need to transfer"
         ins = Risc::SlotToReg.new("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
       else
         raise "not implemented for #{right.class}:#{right}"