small refactor and rename
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@ -13,7 +13,7 @@ module Register
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# but index is left as is.
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# def self.reg_to_byte source , from , to , index
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# from = resolve_to_register from
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# index = resolve_index( to , index)
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# index = resolve_to_index( to , index)
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# to = resolve_to_register to
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# RegToByte.new( source, from , to , index)
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# end
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