small refactor and rename

This commit is contained in:
Torsten Ruger
2016-12-28 18:16:39 +02:00
parent 184f129107
commit 4412eda105
8 changed files with 25 additions and 28 deletions

View File

@ -13,7 +13,7 @@ module Register
# but index is left as is.
# def self.reg_to_byte source , from , to , index
# from = resolve_to_register from
# index = resolve_index( to , index)
# index = resolve_to_index( to , index)
# to = resolve_to_register to
# RegToByte.new( source, from , to , index)
# end

View File

@ -15,10 +15,10 @@ module Register
# Produce a RegToSlot instruction.
# From and to are registers or symbols that can be transformed to a register by resolve_to_register
# index resolves with resolve_index.
# index resolves with resolve_to_index.
def self.reg_to_slot source , from , to , index
from = resolve_to_register from
index = resolve_index( to , index)
index = resolve_to_index( to , index)
to = resolve_to_register to
RegToSlot.new( source, from , to , index)
end

View File

@ -15,11 +15,11 @@ module Register
# Produce a SlotToReg instruction.
# Array and to are registers or symbols that can be transformed to a register by resolve_to_register
# index resolves with resolve_index.
# index resolves with resolve_to_index.
def self.slot_to_reg source , array , index , to
index = resolve_index( array , index)
array = resolve_to_register array
to = resolve_to_register to
index = resolve_to_index( array , index)
array = resolve_to_register( array )
to = resolve_to_register( to )
SlotToReg.new( source , array , index , to)
end
end