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removed the (too) fancy dsl. Also introduce register indirection

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This commit is contained in:
Torsten Ruger
2014-06-07 17:59:44 +03:00
parent 6433a394e7
commit 36f237c633
26 changed files with 128 additions and 161 deletions
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2
lib/arm/compare_instruction.rb
View File

@ -23,7 +23,7 @@ module Arm
immediate = @immediate
arg = @right
if arg.is_a?(Vm::StringConstant)
if arg.is_a?(Vm::ObjectConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
arg = Vm::IntegerConstant.new( arg.position - self.position - 8 )

23
lib/arm/constants.rb
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@ -50,20 +50,21 @@ module Arm
'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
'lr' => 14, 'pc' => 15 }
def reg name
code = reg_code name
raise "no such register #{name}" unless code
Arm::Register.new(name.to_sym , code )
def reg r_name
code = reg_code r_name
raise "no such register #{r_name}" unless code
Arm::Register.new(r_name.to_sym , code )
end
def reg_code name
if name.is_a? Vm::Word
name = "r#{name.register}"
def reg_code r_name
raise "double r #{r_name}" if( :rr1 == r_name)
if r_name.is_a? Vm::Word
r_name = r_name.register_symbol
end
if name.is_a? Fixnum
name = "r#{name}"
if r_name.is_a? Fixnum
r_name = "r#{r_name}"
end
r = REGISTERS[name.to_s]
raise "no reg #{name}" if r == nil
r = REGISTERS[r_name.to_s]
raise "no reg #{r_name}" if r == nil
r
end

4
lib/arm/logic_instruction.rb
View File

@ -25,7 +25,7 @@ module Arm
immediate = @immediate
right = @right
if @left.is_a?(Vm::StringConstant)
if @left.is_a?(Vm::ObjectConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
right = @left.position - self.position - 8
@ -36,7 +36,7 @@ module Arm
right = Vm::IntegerConstant.new( right )
end
if (right.is_a?(Vm::IntegerConstant))
if (right.integer.fits_u8?)
if true #TODO (right.integer.fits_u8?)
# no shifting needed
operand = right.integer
immediate = 1

6
lib/arm/memory_instruction.rb
View File

@ -29,14 +29,14 @@ module Arm
add_offset = @add_offset
arg = @left
arg = "r#{arg.register}".to_sym if( arg.is_a? Vm::Word )
arg = arg.register_symbol if( arg.is_a? Vm::Word )
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
if (arg.is_a?(Symbol)) #symbol is register
rn = arg
if @right
operand = @right
#TODO better test, this operand integer (register) does not work. but sleep first
operand = operand.register if operand.is_a? Vm::Integer
operand = operand.register_symbol if operand.is_a? Vm::Integer
unless( operand.is_a? Symbol)
puts "operand #{operand.inspect}"
if (operand < 0)
@ -51,7 +51,7 @@ module Arm
end
end
end
elsif (arg.is_a?(Vm::StringConstant) ) #use pc relative
elsif (arg.is_a?(Vm::ObjectConstant) ) #use pc relative
rn = :pc
operand = arg.position - self.position - 8 #stringtable is after code
add_offset = 1

11
lib/arm/move_instruction.rb
View File

@ -12,10 +12,11 @@ module Arm
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
# raise inspect if to.is_a?(Vm::Value) and
# from.is_a?(Vm::Value) and
# !@attributes[:shift_lsr] and
# to.register == from.register
raise inspect if to.is_a?(Vm::Value) and
from.is_a?(Vm::Value) and
!@attributes[:shift_lsr] and
to.register_symbol == from.register_symbol
raise "uups " if @to.register_symbol == :rr1
end
# arm intrucions are pretty sensible, and always 4 bytes (thumb not supported)
@ -30,7 +31,7 @@ module Arm
immediate = @immediate
right = @from
if right.is_a?(Vm::StringConstant)
if right.is_a?(Vm::ObjectConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
right = Vm::IntegerConstant.new( right.position - self.position - 8 )