init fell into the ssa tap, fixed

reducing and assuming the same register, buuh
adds a transfer instruction that can hopefully be removed by analysis
This commit is contained in:
2020-03-15 10:39:09 +02:00
parent 5b0c1195e4
commit 3145547315
6 changed files with 20 additions and 17 deletions

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@ -26,9 +26,9 @@ module Risc
Branch, SlotToReg, RegToSlot, SlotToReg, SlotToReg, #60
FunctionReturn, SlotToReg, RegToSlot, Branch, SlotToReg, #65
SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn, #70
Transfer, SlotToReg, SlotToReg, Syscall, NilClass,] #75
assert_equal Parfait::Integer , get_return.class
assert_equal 1 , get_return.value
Transfer, SlotToReg, SlotToReg, Transfer ,Syscall, NilClass,] #75
assert_equal ::Integer , get_return.class
assert_equal 1 , get_return
end
def test_load_entry
call_ins = main_ticks(3)