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fixing assembly

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position code changed and linking too
passes not working
This commit is contained in:
Torsten Ruger
2015-05-24 18:05:20 +03:00
parent 95ac024421
commit 2ccbea04b9
15 changed files with 111 additions and 182 deletions
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33
lib/arm/instructions/move_instruction.rb
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@ -5,15 +5,14 @@ module Arm
def initialize to , from , options = {}
super(options)
@to = to
raise "old code, fix this to use LoadConstant" if from.is_a? Virtual::ObjectConstant
@from = from.is_a?(Fixnum) ? Virtual::IntegerConstant.new(from) : from
@from = from #from.is_a?(Fixnum) ? Virtual::IntegerConstant.new(from) : from
raise "move must have from set #{inspect}" unless from
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@immediate = 0
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
@from = Virtual::IntegerConstant.new( @from ) if( @from.is_a? Fixnum )
@extra = nil
@ -22,11 +21,11 @@ module Arm
# arm intructions are pretty sensible, and always 4 bytes (thumb not supported)
# but not all constants fit into the part of the instruction that is left after the instruction code,
# so large moves have to be split into two instructions.
# so large moves have to be split into two instructions.
# we handle this "transparently", just this instruction looks longer
# alas, full transparency is not achieved as we only know when to use 2 instruction once we know where the
# other object is, and that position is only set after code positions have been determined (in link) and so
# see below in assemble
# other object is, and that position is only set after code positions have been determined (in link) and so
# see below in assemble
def mem_length
@extra ? 8 : 4
end
@ -60,15 +59,15 @@ module Arm
#armv7 operand = (right.integer & 0xFFF)
#armv7 immediate = 1
#armv7 rn = (right.integer >> 12)
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode, but there it is
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode, but there it is
#armv7 @attributes[:opcode] = :tst
raise "No negatives implemented #{right} " if right.integer < 0
# and so it continues: when we notice that the const doesn't fit, first time we raise an
# and so it continues: when we notice that the const doesn't fit, first time we raise an
# error,but set the extra flag, to say the instruction is now 8 bytes
# then on subsequent assemblies we can assemble
unless @extra
@extra = 1
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = Virtual::IntegerConstant.new(right.integer & 0xFFFFFF00)
@ -80,7 +79,7 @@ module Arm
# is to check that the first part is doabe with u8_with_rr AND leaves a u8 remainder
end
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
operand = reg_code(right)
operand = reg_code(right)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.class} , #{self.class}"
@ -89,17 +88,17 @@ module Arm
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barrel action, is already shifted
val |= shift(reg_code(@to) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(reg_code(@to) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
@extra.assemble(io)
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
@ -115,4 +114,4 @@ module Arm
[@to.register]
end
end
end
end