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fix logic instruction arguments

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This commit is contained in:
Torsten Ruger
2014-05-18 12:18:57 +03:00
parent 6abd10f278
commit 2be96dccdc
9 changed files with 69 additions and 61 deletions
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30
lib/arm/arm_machine.rb
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@ -11,27 +11,27 @@ module Arm
class ArmMachine < Vm::CMachine
def integer_less_or_equal block , first , right
block << cmp( first , right: right )
block << cmp( first , right )
Vm::Bool.new
end
def integer_plus block , result , first , right
block << add( result , left: first , :extra => right )
block << add( result , first , right )
result
end
def integer_minus block , result , first , right
block << sub( result , left: first , :extra => right )
block << sub( result , first , right )
result
end
def integer_load block , first , right
block << mov( first , right: right )
block << mov( first , right )
first
end
def integer_move block , first , right
block << mov( first , right: right )
block << mov( first , right )
first
end
@ -82,17 +82,17 @@ module Arm
# And coding it is a bit of a mind leap: it's all about finding a a result that gets the
# remainder smaller than an int. i'll post some links sometime. This is from the arm manual
block.instance_eval do
sub( remainder , left: number , right: 10 )
sub( number , left: number , right: number , shift_lsr: 2)
add( number , left: number , right: number , shift_lsr: 4)
add( number , left: number , right: number , shift_lsr: 8)
add( number , left: number , right: number , shift_lsr: 16)
mov( number , right: number , shift_lsr: 3)
sub( remainder , number , 10 )
sub( number , number , number , shift_lsr: 2)
add( number , number , number , shift_lsr: 4)
add( number , number , number , shift_lsr: 8)
add( number , number , number , shift_lsr: 16)
mov( number , number , shift_lsr: 3)
tmp = Vm::Integer.new( remainder.register + 1)
add( tmp , left: number , right: number , shift_lsl: 2)
sub( remainder , left: remainder , right: tmp , shift_lsl: 1 , update_status: 1)
add( number , left: number, right: 1 , condition_code: :pl )
add( remainder , left: remainder , right: 10 , condition_code: :mi )
add( tmp , number , number , shift_lsl: 2)
sub( remainder , remainder , tmp , shift_lsl: 1 , update_status: 1)
add( number , number, 1 , condition_code: :pl )
add( remainder , remainder , 10 , condition_code: :mi )
end
end

9
lib/arm/logic_instruction.rb
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@ -3,13 +3,12 @@ module Arm
class LogicInstruction < Vm::LogicInstruction
include Arm::Constants
def initialize(first , attributes)
super(first , attributes)
def initialize(result , left , right , attributes)
super(result ,left , right , attributes)
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
@left = @attributes[:left]
raise "Left arg must be given #{inspect}" unless @left
@immediate = 0
end
@ -21,7 +20,7 @@ module Arm
# Build representation for source value
def build
right = @attributes[:right]
right = @right
if @left.is_a?(Vm::StringConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
@ -57,7 +56,7 @@ module Arm
build
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(@operand , 0)
val |= shift(reg_code(@first) , 12)
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(@left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)

10
lib/core/kernel.rb
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@ -43,8 +43,8 @@ module Core
itos_fun = context.program.get_or_create_function(:utoa)
block.instance_eval do
mov( reg1 , right: str_addr ) #move arg up
add( str_addr , left: buffer ) # string to write to
add( str_addr , left: str_addr , right: (buffer.length-3))
add( str_addr , buffer ,nil ) # string to write to
add( str_addr , str_addr , (buffer.length-3))
call( itos_fun , {})
# And now we "just" have to print it, using the write_stdout
add( str_addr , left: buffer ) # string to write to
@ -67,10 +67,10 @@ module Core
Vm::CMachine.instance.div10( block , number , remainder )
# make char out of digit (by using ascii encoding) 48 == "0"
block.instance_eval do
add( remainder , left: remainder , right: 48 )
add( remainder , remainder , 48 )
strb( remainder, right: str_addr )
sub( str_addr, left: str_addr , right: 1 )
cmp( number , right: 0 )
sub( str_addr, str_addr , 1 )
cmp( number , 0 )
callne( function , {} )
end
return function

6
lib/vm/block.rb
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@ -67,11 +67,7 @@ module Vm
# sugar to create instructions easily. Any method with one arg is sent to the machine and the result
# (hopefully an instruction) added as code
def method_missing(meth, *args, &block)
if args.length == 2
add_code CMachine.instance.send(meth , *args)
else
super
end
add_code CMachine.instance.send(meth , *args)
end
end

17
lib/vm/c_machine.rb
View File

@ -48,7 +48,7 @@ module Vm
define_instruction_one(inst , StackInstruction)
end
[:adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub].each do |inst|
define_instruction_one(inst , LogicInstruction)
define_instruction_three(inst , LogicInstruction)
end
[:mov, :mvn].each do |inst|
define_instruction_one(inst , MoveInstruction)
@ -104,11 +104,22 @@ module Vm
# same for two args (left right, from to etc)
def define_instruction_two(inst , clazz , defaults = {} )
clazz = class_for(clazz)
create_method(inst) do |first ,second , options = nil|
create_method(inst) do |left ,right , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
clazz.new(first , second ,options)
clazz.new(left , right ,options)
end
end
# same for three args (result = left right,)
def define_instruction_three(inst , clazz , defaults = {} )
clazz = class_for(clazz)
create_method(inst) do |result , left ,right , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
clazz.new(result, left , right ,options)
end
end

6
lib/vm/instruction.rb
View File

@ -43,8 +43,10 @@ module Vm
end
end
class LogicInstruction < Instruction
def initialize first , options
@first = first
def initialize result , left , right , options
@result = result
@left = left
@right = right
super(options)
end
end