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finally get rid of the fixme in div10

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create (load/reduce) the int once and transfer.
Save a cruicial 2 instructions

Also expanded the variable name possibilities with _self, __const , _1 and _2
This commit is contained in:
Torsten Ruger
2018-08-15 18:18:21 +03:00
parent 15337e10be
commit 252ae6de72
4 changed files with 46 additions and 35 deletions
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39
test/risc/interpreter/calling/test_div10.rb
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@ -14,32 +14,31 @@ module Risc
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, RegToSlot,
SlotToReg, FunctionCall, SlotToReg, SlotToReg, SlotToReg, # 20
SlotToReg, SlotToReg, SlotToReg, LoadData, OperatorInstruction,
LoadData, OperatorInstruction, OperatorInstruction, LoadData, Transfer, # 30
Branch, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction, # 40
OperatorInstruction, LoadData, OperatorInstruction, LoadData, Branch,
Transfer, OperatorInstruction, OperatorInstruction, Transfer, LoadData, # 50
OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, LoadConstant,
SlotToReg, SlotToReg, RegToSlot, Branch, RegToSlot, # 60
RegToSlot, SlotToReg, SlotToReg, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 70
SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot,
SlotToReg, SlotToReg, RegToSlot, Branch, SlotToReg, # 80
SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, # 90
FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall,
NilClass, ]
SlotToReg, FunctionCall, SlotToReg, SlotToReg, Transfer, # 20
Transfer, LoadData, OperatorInstruction, LoadData, OperatorInstruction,
OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction, # 30
Branch, LoadData, Transfer, OperatorInstruction, OperatorInstruction,
LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData, # 40
OperatorInstruction, LoadData, Transfer, OperatorInstruction, Branch,
OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData, # 50
OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg,
RegToSlot, RegToSlot, RegToSlot, Branch, SlotToReg, # 60
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, # 70
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, # 80
Branch, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, # 90
SlotToReg, SlotToReg, Syscall, NilClass, ]
assert_equal 2 , get_return
end
def test_load_space
load_ins = main_ticks 55
load_ins = main_ticks 53
assert_load load_ins, Parfait::Space
end
def test_load_to
to = main_ticks 56
to = main_ticks 54
assert_slot_to_reg to , :r5 , 5 ,:r2
end
def test_load_25
@ -48,7 +47,7 @@ module Risc
assert_equal 25 , @interpreter.get_register(load_ins.register).value
end
def test_return_class
ret = main_ticks(72)
ret = main_ticks(70)
assert_equal FunctionReturn , ret.class
link = @interpreter.get_register( ret.register )
assert_equal Fixnum , link.class