fix all test
and thus all green, two weeks of side branch positioning done (luckily not on arm, but interpreter)
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@ -13,19 +13,20 @@ module Risc
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#show_main_ticks # get output of what is
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check_main_chain [LoadConstant, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
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SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, RegToSlot, SlotToReg, RegToSlot,
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LoadConstant, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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RegToSlot, SlotToReg, FunctionCall, SlotToReg, SlotToReg,
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SlotToReg, SlotToReg, SlotToReg, SlotToReg, LoadData,
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OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, LoadData,
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Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
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OperatorInstruction, OperatorInstruction, LoadData, Transfer, OperatorInstruction,
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OperatorInstruction, LoadData, OperatorInstruction, LoadData, Transfer,
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OperatorInstruction, OperatorInstruction, Transfer, LoadData, OperatorInstruction,
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LoadData, OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg,
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SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg,
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SlotToReg, RegToSlot, SlotToReg, SlotToReg, FunctionReturn,
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SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, RegToSlot, Branch, SlotToReg,
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, LoadConstant,
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SlotToReg, RegToSlot, SlotToReg, FunctionCall, SlotToReg,
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SlotToReg, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
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LoadData, OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction,
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LoadData, Transfer, Branch, OperatorInstruction, OperatorInstruction,
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LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData,
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Transfer, OperatorInstruction, OperatorInstruction, LoadData, OperatorInstruction,
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LoadData, Branch, Transfer, OperatorInstruction, OperatorInstruction,
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Transfer, LoadData, OperatorInstruction, LoadData, OperatorInstruction,
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OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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Branch, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
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SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg,
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RegToSlot, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
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SlotToReg, FunctionReturn, Transfer, Syscall, NilClass]
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assert_equal Parfait::Integer , get_return.class
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@ -33,18 +34,18 @@ module Risc
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end
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def test_load_25
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load_ins = main_ticks 16
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load_ins = main_ticks 17
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assert_equal LoadConstant , load_ins.class
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assert_equal 25 , @interpreter.get_register(load_ins.register).value
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end
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def test_return
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ret = main_ticks(70)
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ret = main_ticks(74)
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assert_equal FunctionReturn , ret.class
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link = @interpreter.get_register( ret.register )
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assert_equal Label , link.class
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end
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def test_sys
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sys = main_ticks(84)
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sys = main_ticks(89)
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assert_equal Syscall , sys.class
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assert_equal :exit , sys.name
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end
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