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move all arm instructions to own folder and fold inheritance

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This commit is contained in:
Torsten Ruger
2014-10-02 22:28:34 +03:00
parent 9923eb0b07
commit 1be71918a5
7 changed files with 158 additions and 36 deletions
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92
lib/arm/instructions/call_instruction.rb Normal file
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module Arm
# There are only three call instructions in arm branch (b), call (bl) and syscall (swi)
# A branch could be called a jump as it has no notion of returning
# The pc is put into the link register to make a return possible
# a return is affected by moving the stored link register into the pc, effectively a branch
# swi (SoftWareInterrupt) or system call is how we call the kernel.
# in Arm the register layout is different and so we have to place the syscall code into register 7
# Registers 0-6 hold the call values as for a normal c call
class CallInstruction < Instruction
include Arm::Constants
def initialize(first, attributes)
super(attributes)
@first = first
opcode = @attributes[:opcode].to_s
if opcode.length == 3 and opcode[0] == "b"
@attributes[:condition_code] = opcode[1,2].to_sym
@attributes[:opcode] = :b
end
if opcode.length == 6 and opcode[0] == "c"
@attributes[:condition_code] = opcode[4,2].to_sym
@attributes[:opcode] = :call
end
@attributes[:update_status] = 0
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
end
def assemble(io)
case @attributes[:opcode]
when :b, :call
arg = @first
#puts "BLAB #{arg.inspect}"
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Virtual::IntegerConstant.new( arg )
end
if arg.is_a?(Virtual::Block) or arg.is_a?(Virtual::CompiledMethod)
#relative addressing for jumps/calls
diff = arg.position - self.position
# but because of the arm "theoretical" 3- stage pipeline, we have to subtract 2 words (fetch/decode)
# But, for methods, this happens to be the size of the object header, so there it balances out, but not blocks
diff -= 8 if arg.is_a?(Virtual::Block)
arg = Virtual::IntegerConstant.new(diff)
end
if (arg.is_a?(Virtual::IntegerConstant))
jmp_val = arg.integer >> 2
packed = [jmp_val].pack('l')
# signed 32-bit, condense to 24-bit
# TODO add check that the value fits into 24 bits
io << packed[0,3]
else
raise "else not coded arg =#{arg}: #{inspect}"
end
io.write_uint8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
when :swi
arg = @first
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Virtual::IntegerConstant.new( arg )
end
if (arg.is_a?(Virtual::IntegerConstant))
packed = [arg.integer].pack('L')[0,3]
io << packed
io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
else
raise "invalid operand argument expected literal not #{arg} #{inspect}"
end
else
raise "Should not be the case #{inspect}"
end
end
def uses
if opcode == :call
@first.args.collect {|arg| arg.register }
else
[]
end
end
def assigns
if opcode == :call
[RegisterReference.new(RegisterMachine.instance.return_register)]
else
[]
end
end
def to_s
"#{opcode} #{@first.to_asm} #{super}"
end
end
end

105
lib/arm/instructions/compare_instruction.rb Normal file
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module Arm
class CompareInstruction < Instruction
include Arm::Constants
def initialize(left , right , attributes)
super(attributes)
@left = left
@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
@immediate = 0
@attributes[:update_status] = 1
@rn = left
@rd = :r0
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
arg = @right
if arg.is_a?(Virtual::ObjectConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
arg = Virtual::IntegerConstant.new( arg.position - self.position - 8 )
rn = :pc
end
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Register::RegisterReference.new( arg )
end
if (arg.is_a?(Virtual::IntegerConstant))
if (arg.fits_u8?)
# no shifting needed
operand = arg.integer
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(arg))
operand = op_with_rot
immediate = 1
raise "hmm"
else
raise "cannot fit numeric literal argument in operand #{arg.inspect}"
end
elsif (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterReference))
operand = arg
immediate = 0
elsif (arg.is_a?(Arm::Shift))
rm_ref = arg.argument
immediate = 0
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
if (arg.type == 'ror' and arg.value.nil?)
# ror #0 == rrx
raise "cannot rotate by zero #{arg} #{inspect}"
end
arg1 = arg.value
if (arg1.is_a?(Virtual::IntegerConstant))
if (arg1.value >= 32)
raise "cannot shift by more than 31 #{arg1} #{inspect}"
end
shift_imm = arg1.value
elsif (arg1.is_a?(Arm::Register))
shift_op val |= 0x1;
shift_imm = arg1.number << 1
elsif (arg.type == 'rrx')
shift_imm = 0
end
operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
else
raise "invalid operand argument #{arg.inspect} , #{inspect}"
end
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference)) ? reg_code(operand) : operand
val = 0 if val == nil
val = shift(val , 0)
raise inspect unless reg_code(@rd)
val |= shift(reg_code(@rd) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.is_a? Constant
ret
end
def assigns
[]
end
def to_s
"#{opcode} #{@left.to_asm} , #{@right.to_asm} #{super}"
end
end
end

85
lib/arm/instructions/logic_instruction.rb Normal file
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module Arm
class LogicInstruction < Instruction
include Arm::Constants
# result = left op right
#
# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
# the result is sort of up in the air, but with Instructions the result must be assigned
def initialize(result , left , right , attributes = {})
super(attributes)
@result = result
@left = left
@right = right.is_a?(Fixnum) ? Virtual::IntegerConstant.new(right) : right
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "Left arg must be given #{inspect}" unless @left
@immediate = 0
end
attr_accessor :result , :left , :right
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
left = @left
operand = @operand
immediate = @immediate
right = @right
if @left.is_a?(Virtual::ObjectConstant)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
right = @left.position - self.position - 8
left = :pc
end
# automatic wrapping, for machine internal code and testing
if( right.is_a? Fixnum )
right = Virtual::IntegerConstant.new( right )
end
if (right.is_a?(Virtual::IntegerConstant))
if (right.fits_u8?)
# no shifting needed
operand = right.integer
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
raise "cannot fit numeric literal argument in operand #{right.inspect}"
end
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.inspect} , #{inspect}"
end
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barral action, is already shifted
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = []
ret << @left.register if @left and not @left.is_a? Constant
ret << @right.register if @right and not @right.is_a?(Constant)
ret
end
def assigns
[@result.register]
end
end
end

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lib/arm/instructions/memory_instruction.rb Normal file
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module Arm
# ADDRESSING MODE 2
# Implemented: immediate offset with offset=0
class MemoryInstruction < Instruction
include Arm::Constants
def initialize result , left , right = nil , attributes = {}
super(attributes)
@result = result
@left = left
@right = right
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "alert" if right.is_a? Virtual::Block
@pre_post_index = 0 #P flag
@add_offset = 0 #U flag
@is_load = opcode.to_s[0] == "l" ? 1 : 0 #L (load) flag
end
def assemble(io )
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
add_offset = @add_offset
arg = @left
arg = arg.symbol if( arg.is_a? ::Register::RegisterReference )
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
if (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterReference)) #symbol is register
rn = arg
if @right
operand = @right
#TODO better test, this operand integer (register) does not work. but sleep first
operand = operand.symbol if operand.is_a? ::Register::RegisterReference
unless( operand.is_a? Symbol)
#puts "operand #{operand.inspect}"
if (operand < 0)
add_offset = 0
#TODO test/check/understand
operand *= -1
else
add_offset = 1
end
if (@operand.abs > 4095)
raise "reference offset too large/small (max 4095) #{arg} #{inspect}"
end
end
end
elsif (arg.is_a?(Virtual::ObjectConstant) ) #use pc relative
rn = :pc
operand = arg.position - self.position - 8 #stringtable is after code
add_offset = 1
if (operand.abs > 4095)
raise "reference offset too large/small (max 4095) #{arg} #{inspect}"
end
elsif( arg.is_a?(Virtual::IntegerConstant) )
#TODO untested brach, probably not working
raise "is this working ?? #{arg} #{inspect}"
@pre_post_index = 1
@rn = pc
@use_addrtable_reloc = true
@addrtable_reloc_target = arg
else
raise "invalid operand argument #{arg.inspect} #{inspect}"
end
#not sure about these 2 constants. They produce the correct output for str r0 , r1
# but i can't help thinking that that is because they are not used in that instruction and
# so it doesn't matter. Will see
add_offset = 1
# TODO to be continued
add_offset = 0 if @attributes[:add_offset]
@pre_post_index = 1
@pre_post_index = 0 if @attributes[:flaggie]
w = 0 #W flag
byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
instuction_class = 0b01 # OPC_MEMORY_ACCESS
if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterReference))
val = reg_code(operand)
@pre_post_index = 0
i = 1 # not quite sure about this, but it gives the output of as. read read read.
else
i = 0 #I flag (third bit)
val = operand
end
val = shift(val , 0 ) # for the test
val |= shift(reg_code(@result) , 12 )
val |= shift(reg_code(rn) , 12+4) #16
val |= shift(@is_load , 12+4 +4)
val |= shift(w , 12+4 +4+1)
val |= shift(byte_access , 12+4 +4+1+1)
val |= shift(add_offset , 12+4 +4+1+1+1)
val |= shift(@pre_post_index, 12+4 +4+1+1+1+1)#24
val |= shift(i , 12+4 +4+1+1+1+1 +1)
val |= shift(instuction_class,12+4 +4+1+1+1+1 +1+1)
val |= shift(cond_bit_code , 12+4 +4+1+1+1+1 +1+1+2)
io.write_uint32 val
end
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.nil?
ret
end
def assigns
[@result.register]
end
end
end

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lib/arm/instructions/move_instruction.rb Normal file
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module Arm
class MoveInstruction < Instruction
include Arm::Constants
def initialize to , from , options = {}
super(options)
@to = to
@from = from.is_a?(Fixnum) ? Virtual::IntegerConstant.new(from) : from
raise "move must have from set #{inspect}" unless from
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
@from = Virtual::IntegerConstant.new( @from ) if( @from.is_a? Fixnum )
@extra = nil
end
attr_accessor :to , :from
# arm intructions are pretty sensible, and always 4 bytes (thumb not supported)
# but not all constants fit into the part of the instruction that is left after the instruction code,
# so large moves have to be split into two instructions.
# we handle this "transparently", just this instruction looks longer
# alas, full transparency is not achieved as we only know when to use 2 instruction once we know where the
# other object is, and that position is only set after code positions have been determined (in link) and so
# see below in assemble
def mem_length
@extra ? 8 : 4
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
right = @from
if right.is_a?(Virtual::ObjectConstant)
r_pos = right.position
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pc pointing to fetch and not execute)
right = Virtual::IntegerConstant.new( r_pos - self.position - 8 )
puts "Position #{r_pos} from #{self.position} = #{right}"
rn = :pc
end
if (right.is_a?(Virtual::IntegerConstant))
if (right.fits_u8?)
# no shifting needed
operand = right.integer
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
# unfortunately i was wrong in thinking the pi is armv7. The good news is the code below implements
# the movw instruction (armv7 for moving a word) and works
#armv7 raise "Too big #{right.integer} " if (right.integer >> 16) > 0
#armv7 operand = (right.integer & 0xFFF)
#armv7 immediate = 1
#armv7 rn = (right.integer >> 12)
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode, but there it is
#armv7 @attributes[:opcode] = :tst
raise "No negatives implemented #{right} " if right.integer < 0
# and so it continues: when we notice that the const doesn't fit, first time we raise an
# error,but set the extra flag, to say the instruction is now 8 bytes
# then on subsequent assemblies we can assemble
unless @extra
@extra = 1
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = Virtual::IntegerConstant.new(right.integer & 0xFFFFFF00)
operand = calculate_u8_with_rr( first )
raise "no fit for #{right}" unless operand
immediate = 1
@extra = ::Register::RegisterMachine.instance.add( to , to , (right.integer & 0xFF) )
#TODO: this is still a hack, as it does not encode all possible values. The way it _should_ be done
# is to check that the first part is doabe with u8_with_rr AND leaves a u8 remainder
end
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterReference))
operand = reg_code(right)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.class} , #{self.class}"
end
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barrel action, is already shifted
val |= shift(reg_code(@to) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
def shift val , by
raise "Not integer #{val}:#{val.class} in #{inspect}" unless val.is_a? Fixnum
val << by
end
def uses
@from.is_a?(Constant) ? [] : [@from.register]
end
def assigns
[@to.register]
end
end
end

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lib/arm/instructions/stack_instruction.rb Normal file
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module Arm
# ADDRESSING MODE 4
class StackInstruction < Instruction
include Arm::Constants
def initialize(first , attributes)
super(attributes)
@first = first
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@attributes[:update_status]= 0
@rn = :r0 # register zero = zero bit pattern
# downward growing, decrement before memory access
# official ARM style stack as used by gas
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
operand = @operand
if (@first.is_a?(Array))
operand = 0
@first.each do |r|
raise "nil register in push, index #{r}- #{inspect}" if r.nil?
operand |= (1 << reg_code(r))
end
else
raise "invalid operand argument #{inspect}"
end
write_base = 1
if (opcode == :push)
pre_post_index = 1
up_down = 0
is_pop = 0
else #pop
pre_post_index = 0
up_down = 1
is_pop = 1
end
instuction_class = 0b10 # OPC_STACK
cond = @attributes[:condition_code].is_a?(Symbol) ? COND_CODES[@attributes[:condition_code]] : @attributes[:condition_code]
@rn = :sp # sp register
#assemble of old
val = operand
val |= (reg_code(@rn) << 16)
val |= (is_pop << 16+4) #20
val |= (write_base << 16+4+ 1)
val |= (@attributes[:update_status] << 16+4+ 1+1)
val |= (up_down << 16+4+ 1+1+1)
val |= (pre_post_index << 16+4+ 1+1+1+1)#24
val |= (instuction_class << 16+4+ 1+1+1+1 +2)
val |= (cond << 16+4+ 1+1+1+1 +2+2)
io.write_uint32 val
end
def is_push?
opcode == :push
end
def is_pop?
!is_push?
end
def uses
is_push? ? regs : []
end
def assigns
is_pop? ? regs : []
end
def regs
@first
end
def to_s
"#{opcode} [#{@first.collect {|f| f.to_asm}.join(',') }] #{super}"
end
end
end