ruby-x/rubyx
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

minor cleanup

Browse Source
This commit is contained in:
Torsten Ruger 2015-06-26 20:00:50 +03:00
parent 37403f1139
commit 108cc8af45
2 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/arm/instructions/call_instruction.rb
View File

@ -33,7 +33,6 @@ module Arm
case @attributes[:opcode]
when :b, :call
arg = @first
puts "BLAB #{arg.class}"
if arg.is_a?(Virtual::Block) or arg.is_a?(Parfait::Method)
#relative addressing for jumps/calls
# but because of the arm "theoretical" 3- stage pipeline,

8
lib/arm/instructions/logic_instruction.rb
View File

@ -57,10 +57,10 @@ module Arm
val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val
end
def shift val , by