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minor cleanup

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This commit is contained in:
Torsten Ruger 2015-06-26 20:00:50 +03:00
parent 37403f1139
commit 108cc8af45
2 changed files with 4 additions and 5 deletions
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1
lib/arm/instructions/call_instruction.rb
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@ -33,7 +33,6 @@ module Arm
case @attributes[:opcode] case @attributes[:opcode]
when :b, :call when :b, :call
arg = @first arg = @first
puts "BLAB #{arg.class}"
if arg.is_a?(Virtual::Block) or arg.is_a?(Parfait::Method) if arg.is_a?(Virtual::Block) or arg.is_a?(Parfait::Method)
#relative addressing for jumps/calls #relative addressing for jumps/calls
# but because of the arm "theoretical" 3- stage pipeline, # but because of the arm "theoretical" 3- stage pipeline,

8
lib/arm/instructions/logic_instruction.rb
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@ -57,10 +57,10 @@ module Arm
val |= shift(reg_code(@result) , 12) val |= shift(reg_code(@result) , 12)
val |= shift(reg_code(left) , 12+4) val |= shift(reg_code(left) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20 val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1) val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 +1+4) val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1) val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2) val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val io.write_uint32 val
end end
def shift val , by def shift val , by