shaves an instruction off resolve_method
by loading nil directly, not space first
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parent
c3b026a180
commit
0a390cc5a9
@ -101,9 +101,6 @@ module Arm
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right = Risc::Position.get(left) - 8
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right = Risc::Position.get(left) - 8
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right -= Risc::Position.get(self).at
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right -= Risc::Position.get(self).at
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if( (right < 0) && ((opcode == :add) || (opcode == :sub)) )
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if( (right < 0) && ((opcode == :add) || (opcode == :sub)) )
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puts "Inverting, was #{right} , new #{-1*right}"
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puts "left #{left.class} #{Risc::Position.get(left)}"
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puts "self #{Risc::Position.get(self)}"
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right *= -1 # this works as we never issue sub only add
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right *= -1 # this works as we never issue sub only add
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set_opcode :sub # so (as we can't change the sign permanently) we can change the opcode
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set_opcode :sub # so (as we can't change the sign permanently) we can change the opcode
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end # and the sign even for sub (beucase we created them)
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end # and the sign even for sub (beucase we created them)
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@ -45,9 +45,8 @@ module Mom
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add_code while_start_label
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add_code while_start_label
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space! << Parfait.object_space
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object! << Parfait.object_space.nil_object
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space << space[:nil_object]
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object - callable_method
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space - callable_method
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if_zero exit_label
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if_zero exit_label
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name! << callable_method[:name]
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name! << callable_method[:name]
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@ -103,7 +103,9 @@ module Risc
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def prerun
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def prerun
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assemblers.each do |asm|
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assemblers.each do |asm|
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asm.instructions.each {|i| i.precheck }
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asm.instructions.each do |ins|
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ins.precheck
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end
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end
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end
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end
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end
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@ -10,16 +10,15 @@ module Risc
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@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
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@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
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LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
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LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
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SlotToReg, Label, LoadConstant, SlotToReg, OperatorInstruction,
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SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
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IsZero, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
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Branch, Label, Transfer, Syscall, Transfer,
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Label, Transfer, Syscall, Transfer, Transfer,
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Transfer, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
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RegToSlot, RegToSlot, Label, RegToSlot, Label,
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RegToSlot, Label, RegToSlot, Label, LoadConstant,
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LoadConstant, SlotToReg, LoadConstant, SlotToReg, SlotToReg,
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SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, RegToSlot, SlotToReg,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
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RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump,
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SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label]
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Label]
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end
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end
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def test_send_instructions
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def test_send_instructions
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@ -27,23 +26,23 @@ module Risc
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end
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end
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def test_sys
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def test_sys
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produced = produce_body
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produced = produce_body
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assert_equal Syscall , produced.next(28).class
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assert_equal Syscall , produced.next(27).class
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assert_equal :exit , produced.next(28).name
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assert_equal :exit , produced.next(27).name
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end
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end
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def test_load_address
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def test_load_address
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produced = produce_body
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produced = produce_body
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assert_equal LoadConstant , produced.next(40).class
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assert_equal LoadConstant , produced.next(41).class
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assert_equal Parfait::CacheEntry , produced.next(40).constant.class
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assert_equal Parfait::Factory , produced.next(41).constant.class
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end
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end
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def test_function_call
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def test_function_call
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produced = produce_body
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produced = produce_body
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assert_equal DynamicJump , produced.next(59).class
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assert_equal DynamicJump , produced.next(58).class
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end
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end
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def test_cache_check
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def test_cache_check
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produced = produce_body
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produced = produce_body
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assert_equal IsZero , produced.next(6).class
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assert_equal IsZero , produced.next(6).class
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assert_equal Label , produced.next(39).class
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assert_equal Label , produced.next(38).class
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assert_equal produced.next(39) , produced.next(6).label
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assert_equal produced.next(38) , produced.next(6).label
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end
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end
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end
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end
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end
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end
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@ -10,17 +10,17 @@ module Risc
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@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
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@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
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LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
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LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
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SlotToReg, Label, LoadConstant, SlotToReg, OperatorInstruction,
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SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
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IsZero, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
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Branch, Label, Transfer, Syscall, Transfer,
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Label, Transfer, Syscall, Transfer, Transfer,
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Transfer, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
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RegToSlot, RegToSlot, Label, RegToSlot, Label,
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RegToSlot, Label, RegToSlot, Label, LoadConstant,
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LoadConstant, SlotToReg, LoadConstant, SlotToReg, SlotToReg,
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SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, RegToSlot, RegToSlot, SlotToReg,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
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RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump,
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SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label,
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Label, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
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SlotToReg, RegToSlot, Branch]
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RegToSlot, Branch]
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end
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end
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def test_return_instructions
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def test_return_instructions
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@ -28,7 +28,7 @@ module Risc
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end
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end
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def test_function_return
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def test_function_return
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produced = produce_body
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produced = produce_body
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assert_equal Branch , produced.next(67).class
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assert_equal Branch , produced.next(66).class
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end
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end
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def test_cache_check
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def test_cache_check
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produced = produce_body
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produced = produce_body
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@ -15,32 +15,30 @@ module Risc
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SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero, # 10
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SlotToReg, SlotToReg, SlotToReg, OperatorInstruction, IsZero, # 10
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SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant,
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SlotToReg, SlotToReg, SlotToReg, Branch, LoadConstant,
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RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, # 20
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RegToSlot, LoadConstant, LoadConstant, SlotToReg, SlotToReg, # 20
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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LoadConstant, OperatorInstruction, IsZero, SlotToReg, OperatorInstruction,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 30
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IsZero, SlotToReg, Branch, Branch, LoadConstant, # 30
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, OperatorInstruction, IsZero,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 40
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SlotToReg, Branch, Branch, LoadConstant, OperatorInstruction, # 40
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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IsZero, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 50
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Branch, Branch, LoadConstant, OperatorInstruction, IsZero, # 50
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 60
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Branch, LoadConstant, OperatorInstruction, IsZero, SlotToReg, # 60
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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OperatorInstruction, IsZero, SlotToReg, Branch, Branch,
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OperatorInstruction, IsZero, Branch, SlotToReg, Branch, # 70
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LoadConstant, OperatorInstruction, IsZero, SlotToReg, OperatorInstruction, # 70
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LoadConstant, SlotToReg, OperatorInstruction, IsZero, SlotToReg,
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IsZero, RegToSlot, LoadConstant, Branch, SlotToReg,
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OperatorInstruction, IsZero, RegToSlot, Branch, LoadConstant, # 80
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LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot, # 80
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SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
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RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
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RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 90
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RegToSlot, LoadConstant, Branch, SlotToReg, RegToSlot, # 90
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SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg,
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SlotToReg, LoadConstant, SlotToReg, DynamicJump, SlotToReg,
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RegToSlot, SlotToReg, LoadConstant, SlotToReg, DynamicJump, # 100
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SlotToReg, LoadData, OperatorInstruction, LoadConstant, SlotToReg, # 100
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SlotToReg, SlotToReg, LoadData, OperatorInstruction, LoadConstant,
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SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, # 110
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SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg, # 110
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SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant,
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RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
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SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 120
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FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, # 120
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SlotToReg, FunctionReturn, SlotToReg, SlotToReg, RegToSlot,
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SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg,
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SlotToReg, SlotToReg, RegToSlot, Branch, Branch, # 130
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RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 130
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SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
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SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer,
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RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, # 140
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SlotToReg, SlotToReg, Syscall, NilClass, ]
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FunctionReturn, Transfer, SlotToReg, SlotToReg, Syscall,
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NilClass, ]
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assert_equal Fixnum , get_return.class
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assert_equal Fixnum , get_return.class
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assert_equal 1 , get_return
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assert_equal 1 , get_return
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end
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end
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@ -57,17 +55,17 @@ module Risc
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end
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end
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def test_dyn
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def test_dyn
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cal = main_ticks(100)
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cal = main_ticks(94)
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assert_equal DynamicJump , cal.class
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assert_equal DynamicJump , cal.class
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end
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end
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def test_return
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def test_return
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ret = main_ticks(141)
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ret = main_ticks(134)
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assert_equal FunctionReturn , ret.class
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assert_equal FunctionReturn , ret.class
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link = @interpreter.get_register( ret.register )
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link = @interpreter.get_register( ret.register )
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assert_equal Fixnum , link.class
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assert_equal Fixnum , link.class
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end
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end
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def test_sys
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def test_sys
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sys = main_ticks(145)
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sys = main_ticks(138)
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assert_equal Syscall , sys.class
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assert_equal Syscall , sys.class
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end
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end
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end
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end
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@ -1,7 +1,7 @@
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require_relative "../helper"
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require_relative "../helper"
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module Risc
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module Risc
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class TestRegisterValue < MiniTest::Test
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class TestRegisterValue1 < MiniTest::Test
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def setup
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def setup
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Parfait.boot!
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Parfait.boot!
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