ion out last changes from grammar update
surprisingly painless, considering it was more or less a rewrite
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@ -183,8 +183,8 @@ module Interpreter
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left = get_register(@instruction.left)
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rr = @instruction.right
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right = get_register(rr)
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case @instruction.operator
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when :add
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case @instruction.operator.to_s
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when "add"
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result = left + right
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when "/"
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result = left / right
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@ -195,7 +195,7 @@ module Interpreter
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when "=="
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result = left == right
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else
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raise "unimplemented #{@instruction.operator} #{@instruction}"
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raise "unimplemented '#{@instruction.operator}' #{@instruction}"
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end
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puts "#{@instruction} == #{result}"
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right = set_register(rr , result)
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@ -2,7 +2,7 @@ module Phisol
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Compiler.class_eval do
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# if - attr_reader :cond, :if_true, :if_false
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def on_if statement
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def on_if_statement statement
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condition , if_true , if_false = *statement
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condition = condition.first
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# to execute the logic as the if states it, the blocks are the other way around
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@ -1,7 +1,7 @@
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module Phisol
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Compiler.class_eval do
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def on_operator statement
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def on_operator_value statement
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puts "operator #{statement.inspect}"
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operator , left_e , right_e = *statement
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left_slot = process(left_e)
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@ -22,7 +22,7 @@ module Phisol
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Virtual::Return.new(:int )
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end
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def on_assign statement
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def on_assignment statement
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puts statement.inspect
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name , value = *statement
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name = name.to_a.first
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@ -1,7 +1,7 @@
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module Phisol
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Compiler.class_eval do
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def on_while statement
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def on_while_statement statement
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#puts statement.inspect
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condition , statements = *statement
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condition = condition.first
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