2016-12-09 12:20:48 +01:00
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|
|
class String
|
2018-04-16 20:24:27 +02:00
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|
|
def camelise
|
2018-04-06 19:54:27 +02:00
|
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|
self.split("_").collect{|str| str.capitalize_first }.join
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|
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end
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|
|
def capitalize_first
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|
|
self[0].capitalize + self[1..-1]
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end
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end
|
2018-04-17 19:26:15 +02:00
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|
|
class Class
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|
|
|
def short_name
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|
|
|
self.name.split("::").last
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|
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end
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end
|
2016-12-09 12:20:48 +01:00
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|
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|
2018-03-26 13:15:48 +02:00
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|
|
# The RiscMachine, is an abstract machine with registers. Think of it as an arm machine with
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|
|
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# normal instruction names. It is not however an abstraction of existing hardware, but only
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|
|
# of that subset that we need.
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|
|
# See risc/Readme
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|
|
|
module Risc
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|
|
end
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|
|
2018-03-13 12:27:24 +01:00
|
|
|
require_relative "risc/padding"
|
2018-05-31 18:01:10 +02:00
|
|
|
require_relative "risc/position/position"
|
2018-05-12 17:32:10 +02:00
|
|
|
require_relative "risc/platform"
|
2017-01-18 19:09:43 +01:00
|
|
|
require "parfait"
|
2018-05-28 13:46:26 +02:00
|
|
|
require_relative "risc/parfait_adapter"
|
2018-03-13 12:27:24 +01:00
|
|
|
require_relative "risc/machine"
|
|
|
|
require_relative "risc/method_compiler"
|
2015-10-22 17:16:29 +02:00
|
|
|
|
|
|
|
class Fixnum
|
|
|
|
def fits_u8?
|
|
|
|
self >= 0 and self <= 255
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
2016-12-09 12:20:48 +01:00
|
|
|
|
2018-03-13 12:27:24 +01:00
|
|
|
require_relative "risc/instruction"
|
2018-04-06 13:21:38 +02:00
|
|
|
require_relative "risc/risc_value"
|
2018-03-29 17:17:19 +02:00
|
|
|
require_relative "risc/text_writer"
|
2018-03-13 12:27:24 +01:00
|
|
|
require_relative "risc/builtin/space"
|
2018-04-06 13:21:38 +02:00
|
|
|
require_relative "risc/builder"
|