2017-01-19 09:02:29 +02:00
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module Risc
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2015-06-21 21:00:16 +03:00
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2016-12-25 18:02:39 +02:00
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# RegToSlot moves data into memory from a register.
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2016-12-25 18:05:39 +02:00
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# SlotToReg moves data into a register from memory.
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2015-06-21 21:00:16 +03:00
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# Both use a base memory (a register)
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# This is because that is what cpu's can do. In programming terms this would be accessing
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2016-12-25 18:02:39 +02:00
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# an element in an array, in the case of RegToSlot setting the register in the array.
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2015-06-21 21:00:16 +03:00
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2017-01-19 09:02:29 +02:00
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# btw: to move data between registers, use RiscTransfer
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2015-06-21 21:00:16 +03:00
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2016-12-25 18:02:39 +02:00
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class RegToSlot < Setter
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2015-06-21 21:00:16 +03:00
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2014-10-03 11:07:18 +03:00
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end
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2015-06-30 09:43:50 +03:00
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2016-12-25 18:02:39 +02:00
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# Produce a RegToSlot instruction.
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2015-06-30 09:43:50 +03:00
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# From and to are registers or symbols that can be transformed to a register by resolve_to_register
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2016-12-28 18:16:39 +02:00
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# index resolves with resolve_to_index.
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2016-12-25 18:02:39 +02:00
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def self.reg_to_slot source , from , to , index
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2015-06-30 09:43:50 +03:00
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from = resolve_to_register from
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2016-12-28 18:16:39 +02:00
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index = resolve_to_index( to , index)
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2015-06-30 09:43:50 +03:00
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to = resolve_to_register to
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2016-12-25 18:02:39 +02:00
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RegToSlot.new( source, from , to , index)
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2015-06-30 09:43:50 +03:00
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end
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2014-10-03 11:07:18 +03:00
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end
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