2015-10-24 10:42:36 +02:00
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module Arm
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class Translator
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2015-10-24 16:11:18 +02:00
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# translator should translate from register instructio set to it's own (arm eg)
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# for each instruction we call the translator with translate_XXX
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# with XXX being the class name.
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# the result is replaced in the stream
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2018-03-11 11:41:15 +01:00
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def translate( instruction )
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2015-10-24 16:11:18 +02:00
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class_name = instruction.class.name.split("::").last
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self.send( "translate_#{class_name}".to_sym , instruction)
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end
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2015-10-24 10:42:36 +02:00
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# don't replace labels
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2018-03-11 11:41:15 +01:00
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def translate_Label( code )
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2015-10-24 10:42:36 +02:00
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nil
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end
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2015-11-14 23:35:12 +01:00
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# arm indexes are
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# in bytes, so *4
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2015-11-15 19:42:07 +01:00
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# if an instruction is passed in we get the index with index function
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2018-03-11 11:41:15 +01:00
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def arm_index( index )
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2017-01-19 08:02:29 +01:00
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index = index.index if index.is_a?(Risc::Instruction)
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2015-11-14 23:35:12 +01:00
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raise "index error 0" if index == 0
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2015-11-15 19:42:07 +01:00
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index * 4
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2015-11-14 23:35:12 +01:00
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end
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2015-10-24 10:42:36 +02:00
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# Arm stores the return address in a register (not on the stack)
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# The register is called link , or lr for short .
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# Maybe because it provides the "link" back to the caller
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# the vm defines a register for the location, so we store it there.
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2016-12-29 20:24:11 +01:00
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def translate_SaveReturn( code )
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2015-11-14 23:35:12 +01:00
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ArmMachine.str( :lr , code.register , arm_index(code) )
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2015-10-24 10:42:36 +02:00
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end
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2018-03-21 11:18:04 +01:00
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def translate_Transfer( code )
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2017-01-19 08:02:29 +01:00
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# Risc machine convention is from => to
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2015-11-19 09:09:55 +01:00
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# But arm has the receiver/result as the first
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ArmMachine.mov( code.to , code.from)
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end
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2016-12-25 17:05:39 +01:00
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def translate_SlotToReg( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.ldr( *slot_args_for(code) )
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2015-10-24 10:42:36 +02:00
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end
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2016-12-25 17:02:39 +01:00
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def translate_RegToSlot( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.str( *slot_args_for(code) )
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end
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def slot_args_for( code )
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2015-11-08 16:10:36 +01:00
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if(code.index.is_a? Numeric)
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2016-12-15 17:21:08 +01:00
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[ code.register , code.array , arm_index(code) ]
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2015-11-08 16:10:36 +01:00
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else
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2016-12-15 17:21:08 +01:00
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[ code.register , code.array , code.index , :shift_lsl => 2]
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2015-11-08 16:10:36 +01:00
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end
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2015-10-24 10:42:36 +02:00
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end
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2016-12-15 17:21:08 +01:00
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def byte_args_for( code )
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args = slot_args_for( code )
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args.pop if(code.index.is_a? Numeric)
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args
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end
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2016-12-25 17:11:58 +01:00
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def translate_ByteToReg code
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2016-12-15 17:21:08 +01:00
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ArmMachine.ldrb( *byte_args_for(code) )
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2015-11-19 09:09:55 +01:00
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end
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2016-12-25 17:11:58 +01:00
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def translate_RegToByte code
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2016-12-15 17:21:08 +01:00
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ArmMachine.strb( *byte_args_for(code) )
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2015-11-19 09:09:55 +01:00
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end
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2015-10-24 10:42:36 +02:00
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def translate_FunctionCall code
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2015-11-14 23:35:12 +01:00
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ArmMachine.b( code.method.instructions )
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2015-10-24 10:42:36 +02:00
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end
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def translate_FunctionReturn code
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2015-11-14 23:35:12 +01:00
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ArmMachine.ldr( :pc , code.register , arm_index(code) )
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2015-10-24 10:42:36 +02:00
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end
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def translate_LoadConstant code
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constant = code.constant
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2017-01-19 08:02:29 +01:00
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if constant.is_a?(Parfait::Object) or constant.is_a?(Symbol) or constant.is_a?(Risc::Label)
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2015-10-24 10:42:36 +02:00
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return ArmMachine.add( code.register , constant )
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else
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2015-11-03 15:20:25 +01:00
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return ArmMachine.mov( code.register , constant )
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2015-10-24 10:42:36 +02:00
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end
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end
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2015-11-12 19:02:14 +01:00
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def translate_OperatorInstruction code
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left = code.left
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right = code.right
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case code.operator.to_s
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when "+"
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c = ArmMachine.add(left , left , right)
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when "-"
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c = ArmMachine.sub(left , left , right)
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when "&"
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c = ArmMachine.and(left , left , right)
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when "|"
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c = ArmMachine.orr(left , left , right)
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when "*"
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c = ArmMachine.mul(left , right , left) #arm rule about left not being result, lukily commutative
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2015-11-13 23:20:03 +01:00
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when ">>"
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c = ArmMachine.mov(left , left , :shift_asr => right) #arm rule about left not being result, lukily commutative
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when "<<"
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c = ArmMachine.mov(left , left , :shift_lsl => right) #arm rule about left not being result, lukily commutative
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2015-11-12 19:02:14 +01:00
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else
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raise "unimplemented '#{code.operator}' #{code}"
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end
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c
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end
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2015-10-24 10:42:36 +02:00
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# This implements branch logic, which is simply assembler branch
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#
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# The only target for a call is a Block, so we just need to get the address for the code
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# and branch to it.
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def translate_Branch code
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2015-10-24 16:11:18 +02:00
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ArmMachine.b( code.label )
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2015-10-24 10:42:36 +02:00
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end
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2015-10-24 16:11:18 +02:00
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2015-11-13 23:20:03 +01:00
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def translate_IsPlus code
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ArmMachine.bpl( code.label)
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end
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def translate_IsMinus code
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ArmMachine.bmi( code.label)
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end
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def translate_IsZero code
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ArmMachine.beq( code.label)
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end
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def translate_IsOverflow code
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ArmMachine.bvs( code.label)
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end
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2015-10-24 10:42:36 +02:00
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def translate_Syscall code
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call_codes = { :putstring => 4 , :exit => 1 }
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int_code = call_codes[code.name]
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raise "Not implemented syscall, #{code.name}" unless int_code
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send( code.name , int_code )
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end
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def putstring int_code
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2015-11-16 17:03:29 +01:00
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codes = ArmMachine.add( :r1 , :r1 , 12 ) # adjust for object header
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2015-11-15 10:28:16 +01:00
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codes.append ArmMachine.mov( :r0 , 1 ) # write to stdout == 1
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2015-10-24 10:42:36 +02:00
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syscall(int_code , codes )
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end
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def exit int_code
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2017-01-19 08:02:29 +01:00
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codes = ArmMachine.ldr( :r0 , :r0 , arm_index(Risc.resolve_to_index(:Message , :return_value)) )
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2015-10-24 10:42:36 +02:00
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syscall int_code , codes
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end
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private
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# syscall is always triggered by swi(0)
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# The actual code (ie the index of the kernel function) is in r7
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def syscall int_code , codes
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codes.append ArmMachine.mov( :r7 , int_code )
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codes.append ArmMachine.swi( 0 )
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codes
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end
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end
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end
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