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rubyx/lib/risc/builtin/integer.rb

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transformations according to todays post
2014-06-13 23:19:12 +02:00
#integer related kernel functions
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
module Risc
finally scoping builtin to register had put this off because it breaks history but now the references to register stuff which builtin is off course full of, become much shorter
2015-06-29 20:03:58 +02:00
module Builtin
module Integer
module ClassMethods
stop pinning self and frame before: r0-message , r1-self , r2-frame , r3-new_message , r4 + tmps now: r0-message , r1-new_message , r2 + tmps programs got smaller, less fuss also fix in return implementation that got the address from the wrong message
2015-10-18 16:20:19 +02:00
include AST::Sexp
fix test result, but not test yet
2015-08-07 15:46:55 +02:00
serious bit fiddling, div10 using shift magic forgot that arm has no division (or respectively only later models have) many magic formulae out there, none seem to work 1000% on the interpreter. some big 0 ending numbers are 1 off.
2015-11-13 19:46:27 +01:00
def mod4 context
stash old vm moving on to getting mom to work and can’t have both interpreter and elf broke, about 100 tests went
2018-03-11 12:32:42 +01:00
compiler = Risc::MethodCompiler.create_method(:Integer,:mod4 ).init_method
use compiler to generate methods and their instructions
2015-10-28 20:37:42 +01:00
return compiler.method
plus function, indentation
2015-08-05 17:49:37 +02:00
end
change args argument to create method to be hash was array and didn’t carry types and names
2015-11-11 19:41:02 +01:00
def putint context
stash old vm moving on to getting mom to work and can’t have both interpreter and elf broke, about 100 tests went
2018-03-11 12:32:42 +01:00
compiler = Risc::MethodCompiler.create_method(:Integer,:putint ).init_method
use compiler to generate methods and their instructions
2015-10-28 20:37:42 +01:00
return compiler.method
plus function, indentation
2015-08-05 17:49:37 +02:00
end
change args argument to create method to be hash was array and didn’t carry types and names
2015-11-11 19:41:02 +01:00
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
def div10 context
s = "div_10"
stash old vm moving on to getting mom to work and can’t have both interpreter and elf broke, about 100 tests went
2018-03-11 12:32:42 +01:00
compiler = Risc::MethodCompiler.create_method(:Integer,:div10 ).init_method
rename self to receiver just because it is a keyword and can’t be used
2018-03-14 15:56:13 +01:00
me = compiler.add_known( :receiver )
tmp = compiler.add_known( :receiver )
q = compiler.add_known( :receiver )
stash old vm moving on to getting mom to work and can’t have both interpreter and elf broke, about 100 tests went
2018-03-11 12:32:42 +01:00
const = compiler.use_reg :Integer , 1
compiler.add_load_constant( s, 1 , const )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# int tmp = self >> 1
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , tmp , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# int q = self >> 2
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 2 , const)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , q , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# q = q + tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , q , tmp )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = q >> 4
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 4 , const)
compiler.add_transfer( s, q , tmp)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , tmp , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# q = q + tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , q , tmp )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = q >> 8
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 8 , const)
compiler.add_transfer( s, q , tmp)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , tmp , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# q = q + tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , q , tmp )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = q >> 16
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 16 , const)
compiler.add_transfer( s, q , tmp)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , tmp , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# q = q + tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , q , tmp )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# q = q >> 3
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 3 , const)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , q , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = q * 10
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 10 , const)
compiler.add_transfer( s, q , tmp)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "*" , tmp , const)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = self - tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "-" , me , tmp )
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_transfer( s , me , tmp)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = tmp + 6
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 6 , const)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , tmp , const )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# tmp = tmp >> 4
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_load_constant( s , 4 , const)
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , ">>" , tmp , const )
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
# return q + tmp
rename register to risc seems to fit the layer much better as we really have a very reduced instruction set
2017-01-19 08:02:29 +01:00
compiler.add_code Risc.op( s , "+" , q , tmp )
tighter integration with factory methods for adding code define methods to collapse the code Register. in add_code Register.factory_method most instructions done, except op and branch that are rare
2016-12-28 19:37:54 +01:00
compiler.add_reg_to_slot( s , q , :message , :return_value)
implement the div10 as assembler easy after the some version worked because it’s not arm it probably twice as long as need be better (any?) optimisation would take care of that still, nice to see it works
2015-11-21 13:20:25 +01:00
return compiler.method
end
finally scoping builtin to register had put this off because it breaks history but now the references to register stuff which builtin is off course full of, become much shorter
2015-06-29 20:03:58 +02:00
end
extend ClassMethods
change to module style like other modules in this dir
2014-09-11 14:08:56 +02:00
end
transformations according to todays post
2014-06-13 23:19:12 +02:00
end
fix method seperation Since Compiled method split into Method and CompiledMethodInfo (parfait/vm) lots of call syntax changes
2015-05-24 12:31:33 +02:00
end
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