2017-01-14 19:28:44 +02:00
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module Vm
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2016-12-09 14:17:01 +02:00
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module OperatorExpression
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2015-10-07 10:05:34 +03:00
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2016-03-07 11:55:28 +02:00
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def on_OperatorExpression statement
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2016-12-09 14:17:01 +02:00
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# operator , left_e , right_e = *statement
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2015-10-15 09:32:47 +03:00
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# left and right must be expressions. Expressions return a register when compiled
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2016-03-07 11:55:28 +02:00
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left_reg = process(statement.left_expression)
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right_reg = process(statement.right_expression)
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2017-01-19 09:02:29 +02:00
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raise "Not register #{left_reg}" unless left_reg.is_a?(Risc::RiscValue)
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raise "Not register #{right_reg}" unless right_reg.is_a?(Risc::RiscValue)
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add_code Risc::OperatorInstruction.new(statement,statement.operator,left_reg,right_reg)
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2015-10-15 09:32:47 +03:00
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return left_reg # though this has wrong value attached
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2015-09-19 16:28:41 +03:00
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end
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end
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end
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