2017-01-19 08:02:29 +01:00
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module Risc
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2015-08-04 21:01:20 +02:00
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2018-04-19 21:13:52 +02:00
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def self.operators
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[:+, :-, :>>, :<<, :*, :&, :|]
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end
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2018-03-24 16:53:27 +01:00
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# Destructive operator instructions on the two registers given
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#
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# left = left OP right
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#
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# With OP being the normal logical and mathematical operations provided by
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# cpus. Ie "+" , "-", ">>", "<<", "*", "&", "|"
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#
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2015-08-04 21:01:20 +02:00
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class OperatorInstruction < Instruction
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2018-03-24 16:53:27 +01:00
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def initialize( source , operator , left , right )
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2015-08-04 21:01:20 +02:00
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super(source)
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@operator = operator
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2018-04-19 21:13:52 +02:00
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raise "unsuported operator :#{operator}:" unless Risc.operators.include?(operator)
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2015-08-04 21:01:20 +02:00
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@left = left
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@right = right
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2018-04-05 11:22:40 +02:00
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raise "Not register #{left}" unless RiscValue.look_like_reg(left)
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raise "Not register #{right}" unless RiscValue.look_like_reg(right)
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2015-08-04 21:01:20 +02:00
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end
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2015-08-07 15:46:55 +02:00
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attr_reader :operator, :left , :right
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2015-08-04 21:01:20 +02:00
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def to_s
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2018-03-22 17:38:19 +01:00
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class_source "#{left} #{operator} #{right}"
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2015-08-04 21:01:20 +02:00
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end
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2015-11-21 13:17:54 +01:00
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end
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2018-03-24 16:53:27 +01:00
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def self.op( source , operator , left , right )
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OperatorInstruction.new( source , operator , left , right )
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2015-08-04 21:01:20 +02:00
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end
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end
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