2017-01-14 18:28:44 +01:00
|
|
|
module Vm
|
2016-12-09 13:17:01 +01:00
|
|
|
module OperatorExpression
|
2015-10-07 09:05:34 +02:00
|
|
|
|
2016-03-07 10:55:28 +01:00
|
|
|
def on_OperatorExpression statement
|
2016-12-09 13:17:01 +01:00
|
|
|
# operator , left_e , right_e = *statement
|
2015-10-15 08:32:47 +02:00
|
|
|
# left and right must be expressions. Expressions return a register when compiled
|
2016-03-07 10:55:28 +01:00
|
|
|
left_reg = process(statement.left_expression)
|
|
|
|
right_reg = process(statement.right_expression)
|
2017-01-19 08:02:29 +01:00
|
|
|
raise "Not register #{left_reg}" unless left_reg.is_a?(Risc::RiscValue)
|
|
|
|
raise "Not register #{right_reg}" unless right_reg.is_a?(Risc::RiscValue)
|
|
|
|
add_code Risc::OperatorInstruction.new(statement,statement.operator,left_reg,right_reg)
|
2015-10-15 08:32:47 +02:00
|
|
|
return left_reg # though this has wrong value attached
|
2015-09-19 15:28:41 +02:00
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|