2015-07-23 12:15:44 +02:00
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2015-07-23 19:09:19 +02:00
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require "eventable"
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2015-07-23 12:15:44 +02:00
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class Interpreter
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2015-07-26 17:27:12 +02:00
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# fire events for changed pc and register contents
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2015-07-23 19:09:19 +02:00
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include Eventable
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2015-07-23 12:15:44 +02:00
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2015-07-26 17:27:12 +02:00
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# current instruction or pc
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attr_reader :instruction
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# an (arm style) link register. store the return address to return to
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attr_reader :link
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# current executing block. since this is not a hardware simulator this is luxury
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attr_reader :block
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# the registers, 12
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2015-07-26 12:59:58 +02:00
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attr_reader :registers
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2015-07-26 17:27:12 +02:00
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# collect the output
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attr_reader :stdout
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2015-07-23 12:15:44 +02:00
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def initialize
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@stdout = ""
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2015-07-24 16:21:13 +02:00
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@registers = {}
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(0...12).each do |r|
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set_register "r#{r}".to_sym , "undefined"
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end
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2015-07-23 12:15:44 +02:00
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end
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2015-07-23 19:09:19 +02:00
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2015-07-24 12:56:31 +02:00
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def start bl
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set_block bl
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end
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def set_block bl
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return if @block == bl
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raise "Error, nil block" unless bl
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old = @block
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@block = bl
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trigger(:block_changed , old , bl)
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set_instruction bl.codes.first
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end
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def set_instruction i
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return if @instruction == i
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raise "Error, nil instruction" unless i
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old = @instruction
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@instruction = i
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trigger(:instruction_changed, old , i)
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end
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def get_register( reg )
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reg = reg.symbol if reg.is_a? Register::RegisterReference
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raise "Not a register #{reg}" unless Register::RegisterReference.look_like_reg(reg)
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@registers[reg]
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end
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def set_register reg , val
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old = get_register( reg ) # also ensures format
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return if old === val
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reg = reg.symbol if reg.is_a? Register::RegisterReference
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@registers[reg] = val
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trigger(:register_changed, reg , old , val)
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end
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def tick
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return unless @instruction
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name = @instruction.class.name.split("::").last
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fetch = send "execute_#{name}"
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return unless fetch
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2015-07-24 14:48:12 +02:00
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fetch_next_intruction
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end
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def fetch_next_intruction
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if(@instruction != @block.codes.last)
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set_instruction @block.codes[ @block.codes.index(@instruction) + 1]
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else
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next_b = @block.method.source.blocks.index(@block) + 1
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set_block @block.method.source.blocks[next_b]
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end
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end
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2015-07-24 20:15:47 +02:00
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def object_for reg
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id = get_register(reg)
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Virtual.machine.objects[id]
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end
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# Instruction interpretation starts here
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def execute_Branch
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target = @instruction.block
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set_block target
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false
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end
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def execute_LoadConstant
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to = @instruction.register
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value = @instruction.constant.object_id
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set_register( to , value )
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true
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end
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def execute_GetSlot
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object = object_for( @instruction.array )
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value = object.internal_object_get( @instruction.index )
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value = value.object_id unless value.is_a? Integer
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set_register( @instruction.register , value )
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true
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end
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def execute_SetSlot
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value = object_for( @instruction.register )
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object = object_for( @instruction.array )
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object.internal_object_set( @instruction.index , value )
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true
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end
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def execute_RegisterTransfer
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value = get_register @instruction.from
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set_register @instruction.to , value
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true
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end
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def execute_FunctionCall
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@link = [@block , @instruction]
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next_block = @instruction.method.source.blocks.first
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set_block next_block
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false
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end
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def execute_SaveReturn
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object = object_for @instruction.register
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raise "save return has nothing to save" unless @link
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object.internal_object_set @instruction.index , @link
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true
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end
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def execute_Syscall
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name = @instruction.name
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case name
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when :putstring
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str = object_for( :r1 ) # should test length, ie r2
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raise "NO string for putstring #{str}" unless str.is_a? Symbol
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@stdout += str.to_s
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when :exit
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@instruction = nil
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return false
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else
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raise "un-implemented syscall #{name}"
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end
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true
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end
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def execute_FunctionReturn
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object = object_for( @instruction.register )
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#wouldn't need to assign to link, but makes tsting easier
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@link = object.internal_object_get( @instruction.index )
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@block , @instruction = @link
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# we jump back to the call instruction. so it is as if the call never happened and we continue
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true
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end
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end
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