small fixes
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@ -74,7 +74,7 @@ The Register machine layer is a relatively close abstraction of risc hardware, b
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quirks.
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The register machine has registers, indexed addressing, operators, branches and everything
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needed for the next layer. It doesn't not try to abstract every possible machine feature
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needed for the next layer. It does not try to abstract every possible machine feature
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(like llvm), but rather "objectifies" the risc view to provide what is needed for the typed
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layer, the next layer up.
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