ruby-x.github.io/app/views/pages/arm/target.html.haml

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2018-04-10 17:39:03 +02:00
!!! Strict
!!! XML
%html{:lang => "en", "xml:lang" => "en", :xmlns => "http://www.w3.org/1999/xhtml"}
%head
%meta{:content => "text/html; charset=UTF-8", "http-equiv" => "Content-Type"}/
%meta{:content => "text/css", "http-equiv" => "Content-Style-Type"}/
%title target
%link{:href => "./target/target.css", :rel => "stylesheet", :type => "text/css"}/
/[if IE] <script type="text/javascript" src="./target/excanvas-compiled.js"></script>
%script{:src => "./target/target.js", :type => "text/javascript"} :cdata
%body
%div{:style => "margin:1ex;"}
%div{:style => "width:100%"}
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 1
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%div{:style => "position:absolute;top:281.92pt;left:531.52pt;z-index:111;"} s
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
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%div{:style => "position:absolute;top:340.72pt;left:194.68pt;z-index:84;letter-spacing:.001em;"} The ARM Instruction Set
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:58;"} The ARM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:766.12pt;z-index:58;"} 1
%div{:style => "width:100%"}
%hr/
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%b Page 2
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%div{:style => "position:absolute;top:70.3622pt;left:260.68pt;z-index:75;letter-spacing:.001em;"} Processor Modes
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%span.fmt-4 *
The ARM has six operating modes:
%span{:style => "white-space:pre;"}
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%span.fmt-6 U
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(unprivileged mode under which most tasks run)
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%span.fmt-6 F
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(entered when a high priority (fast) interrupt is raised)
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%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:282;letter-spacing:-.002em;"}
%span.fmt-6 I
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(entered when a low priority (normal) interrupt is raised)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:346;letter-spacing:-.002em;"}
%span.fmt-6 S
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(entered on reset and when a Software Interrupt instr
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.33pt;left:156.76pt;z-index:365;"} executed)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:320.01pt;left:137.32pt;z-index:412;letter-spacing:-.003em;"}
%span.fmt-6 A
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(used to handle memory access violations)
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(used to handle undefined instructions)
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ARM Architecture Version 4 adds a seventh mode:
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%span.fmt-6 S
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(privileged mode using the same registers as user mode)
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:168.57pt;left:107.56pt;z-index:61;"} *
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:12;letter-spacing:.002em;"} RM I
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%div{:style => "position:absolute;top:70.3621pt;left:294.04pt;z-index:664;letter-spacing:.001em;"} The Registers
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%div{:style => "position:absolute;top:168.57pt;left:131.8pt;z-index:122;"} ARM has 37 registers in total, all of which are 32-bits long.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:197.25pt;left:146.44pt;z-index:150;letter-spacing:-.004em;"} • 1 dedicated program counter
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%div{:style => "position:absolute;top:225.93pt;left:146.44pt;z-index:194;letter-spacing:-.003em;"} • 1 dedicated current program status register
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%div{:style => "position:absolute;top:254.61pt;left:146.44pt;z-index:237;letter-spacing:-.003em;"} • 5 dedicated saved program status registers
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%div{:style => "position:absolute;top:283.29pt;left:146.44pt;z-index:266;letter-spacing:-.004em;"} • 30 general purpose registers
%img{:alt => "__rendered_path__59", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:59;"}/
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%div{:style => "position:absolute;top:311.97pt;left:131.8pt;z-index:334;"} However these are arranged into several banks, with the accessible
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%div{:style => "position:absolute;top:333.45pt;left:131.8pt;z-index:398;"} bank being governed by the processor mode. Each mode can access
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%div{:style => "position:absolute;top:362.13pt;left:146.44pt;z-index:435;letter-spacing:-.003em;"} • a particular set of r0-r12 registers
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%div{:style => "position:absolute;top:390.93pt;left:146.44pt;z-index:496;letter-spacing:-.002em;"} • a particular r13 (the stack pointer) and r14 (link register)
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%div{:style => "position:absolute;top:419.61pt;left:146.44pt;z-index:522;letter-spacing:-.004em;"} • r15 (the program counter)
%img{:alt => "__rendered_path__665", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:665;"}/
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%div{:style => "position:absolute;top:448.29pt;left:146.44pt;z-index:565;letter-spacing:-.003em;"} • cpsr (the current program status register)
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%div{:style => "position:absolute;top:476.97pt;left:131.8pt;z-index:601;"} and privileged modes can also access
%img{:alt => "Image_34_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:60;"}/
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%div{:style => "position:absolute;top:505.65pt;left:146.44pt;z-index:651;letter-spacing:-.002em;"} • a particular spsr (saved program status register)
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:57;letter-spacing:-.001em;"} struction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:204.88pt;z-index:56;letter-spacing:-.001em;"} - ARM University Program - V1.0
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%div{:style => "position:absolute;top:160.09pt;left:569.92pt;z-index:476;"} Registers in use
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%div{:style => "position:absolute;top:416.91pt;left:597.76pt;z-index:135;"} r15 (pc)
%img{:alt => "__rendered_path__442", :src => "./target/80fe001c8b3881dff1b7ee386c351605.png", :style => "position:absolute;left:564.76pt;top:410.56pt;width:14pt;height:10pt;z-index:442;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:448.71pt;left:604.24pt;z-index:108;letter-spacing:.002em;"} cpsr
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:462.99pt;left:598.36pt;z-index:102;letter-spacing:-.002em;"} spsr_fiq
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
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%div{:style => "position:absolute;top:552.8pt;left:766.12pt;z-index:57;"} 5
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%hr/
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%b Page 6
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%div{:style => "position:absolute;top:269.85pt;left:684.88pt;z-index:367;"} t
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
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%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
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%div{:style => "position:absolute;top:49.3622pt;left:174.4pt;z-index:86;letter-spacing:.001em;"} Accessing Registers using
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:261.88pt;z-index:102;letter-spacing:.001em;"} ARM Instructions
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:150;letter-spacing:-.001em;"}
%span.fmt-15 *
No breakdown of currently accessible registers.
%span.fmt-15{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:195;letter-spacing:-.003em;"} • All instructions can access r0-r14 directly.
%span.fmt-15{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:239;letter-spacing:-.003em;"} • Most instructions also allow use of the PC.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:98.4381pt;z-index:295;"}
%span.fmt-15 *
Specific instructions to allow access to CPSR and SPSR.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:98.438pt;z-index:366;"}
%span.fmt-15 *
Note : When in a privileged mode, it is also possible to load / store
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.33pt;left:122.68pt;z-index:421;"} (banked out) user mode registers to or from memory.
%span.fmt-15{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:320.01pt;left:137.32pt;z-index:445;letter-spacing:-.005em;"} • See later for details.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:49.3622pt;left:144.16pt;z-index:88;letter-spacing:.001em;"} The Program Status Registers
%img{:alt => "__rendered_path__512", :src => "./target/e8df83956786a8bf4a55d7dc64af2db8.png", :style => "position:absolute;left:582.1pt;top:209.04pt;width:35pt;height:26.9pt;z-index:512;"}/
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%div{:style => "position:absolute;top:91.242pt;left:252.28pt;z-index:104;letter-spacing:.001em;"} (CPSR and SPSRs)
%img{:alt => "__rendered_path__514", :src => "./target/bfc0ec4f45fa5d691e048c7e88fbbab4.png", :style => "position:absolute;left:301.9pt;top:207.98pt;width:1.1pt;height:8.7pt;z-index:514;"}/
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N
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%div{:style => "position:absolute;top:276.23pt;left:99.2789pt;z-index:150;"} Copies of the ALU status flags (latched if the
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%div{:style => "position:absolute;top:293.27pt;left:99.279pt;z-index:183;"} instruction has the "S" bit set).
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%div{:style => "position:absolute;top:329.85pt;left:78.1581pt;z-index:507;"} * Condition Code Flags
%div{:style => "position:absolute;top:329.85pt;left:438.64pt;z-index:507;letter-spacing:.001em;"}
%span{:style => "position:relative;left:0pt;top:-3pt;"} *
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N =
= succeed "egative" do
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%span{:style => "position:relative;left:0pt;top:-8pt;"} I
%span{:style => "position:relative;left:0pt;top:-8pt;"} Q
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%span{:style => "white-space:pre;"}
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C = ALU operation
= succeed "arried" do
%span.fmt-19 C
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%span.fmt-19{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:419.13pt;left:119.08pt;z-index:419;"}
%span.fmt-18 V
%span.fmt-18
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%span.fmt-18
= succeed "V" do
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%span.fmt-18 w
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%span.fmt-18 d
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%span{:style => "position:relative;left:0pt;top:-8pt;"} (
%span{:style => "position:relative;left:0pt;top:-8pt;"} A
%span{:style => "position:relative;left:0pt;top:-8pt;"} r
%span{:style => "position:relative;left:0pt;top:-8pt;"} c
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%span{:style => "position:relative;left:0pt;top:-8pt;"} c
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%span{:style => "position:relative;left:0pt;top:-8pt;"} u
%span{:style => "position:relative;left:0pt;top:-8pt;"} r
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%span{:style => "position:relative;left:0pt;top:-8pt;"} 4
%span{:style => "position:relative;left:0pt;top:-8pt;"} T
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%span{:style => "position:relative;left:0pt;top:-8pt;"} l
%span{:style => "position:relative;left:0pt;top:-8pt;"} y
%span{:style => "position:relative;left:0pt;top:-8pt;"} )
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:431.97pt;left:473.56pt;z-index:448;"} T = 0, Processor in ARM state
%img{:alt => "__rendered_path__514", :src => "./target/bfc0ec4f45fa5d691e048c7e88fbbab4.png", :style => "position:absolute;left:477.58pt;top:207.98pt;width:1.1pt;height:8.7pt;z-index:514;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:461.61pt;left:80.1996pt;z-index:559;"}
%span.fmt-19 *
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%span.fmt-19 t
%span.fmt-19 s
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%span{:style => "position:relative;left:0pt;top:-9pt;"} T
%span{:style => "position:relative;left:0pt;top:-9pt;"}
%span{:style => "position:relative;left:0pt;top:-9pt;"} =
%span{:style => "position:relative;left:0pt;top:-9pt;"}
%span{:style => "position:relative;left:0pt;top:-9pt;"} 1
%span{:style => "position:relative;left:0pt;top:-9pt;"} ,
%span{:style => "position:relative;left:0pt;top:-9pt;"}
%span{:style => "position:relative;left:0pt;top:-9pt;"} P
%span{:style => "position:relative;left:0pt;top:-9pt;"} r
%span{:style => "position:relative;left:0pt;top:-9pt;"} o
%span{:style => "position:relative;left:0pt;top:-9pt;"} c
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%span{:style => "position:relative;left:0pt;top:-9pt;"} s
%span{:style => "position:relative;left:0pt;top:-9pt;"} s
%span{:style => "position:relative;left:0pt;top:-9pt;"} o
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%span{:style => "position:relative;left:0pt;top:-9pt;"} u
%span{:style => "position:relative;left:0pt;top:-9pt;"} m
%span{:style => "position:relative;left:0pt;top:-9pt;"} b
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:482.61pt;left:115.12pt;z-index:592;"}
%span.fmt-19> M
[4:0] define the processor mode.
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%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:57;"} The ARM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:766.12pt;z-index:57;"} 7
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 8
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-23{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:433.24pt;z-index:492;letter-spacing:.001em;"} n
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:467.68pt;z-index:494;letter-spacing:.001em;"} F
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:102.64pt;z-index:10;"} M
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:185.32pt;z-index:24;letter-spacing:.001em;"} S
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:234.28pt;z-index:31;"} M
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:248.2pt;z-index:33;"} U
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
%span.fmt-22{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:202.42pt;left:113.08pt;z-index:106;letter-spacing:.001em;"} Flag
%img{:alt => "__rendered_path__107", :src => "./target/0d9e8bea7d53d26dd096547d916bbc38.png", :style => "position:absolute;left:113.08pt;top:219.08pt;width:34pt;height:3pt;z-index:107;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:240.94pt;left:113.08pt;z-index:115;letter-spacing:.001em;"} Negative
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:260.14pt;left:113.08pt;z-index:165;"} (N=1)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.98pt;left:113.08pt;z-index:216;"} Zero
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:337.18pt;left:113.08pt;z-index:271;letter-spacing:.001em;"} (Z=1)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:375.7pt;left:113.08pt;z-index:276;"} Carry
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:395.02pt;left:113.08pt;z-index:335;"} (C=1)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:433.54pt;left:113.08pt;z-index:368;letter-spacing:.001em;"} oVerflow
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:452.74pt;left:113.08pt;z-index:416;"} (V=1)
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:23;letter-spacing:.001em;"} Instruction
%img{:alt => "__rendered_path__61", :src => "./target/78c0528c83b82ff6b9b873e8dc84fcd4.png", :style => "position:absolute;left:113.08pt;top:180.56pt;width:76pt;height:3pt;z-index:61;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:193.72pt;z-index:28;letter-spacing:-.001em;"} et -
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:216.28pt;z-index:30;letter-spacing:-.013em;"} AR
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:244.72pt;z-index:32;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:275.92pt;z-index:491;letter-spacing:.001em;"} Conditio
%span.fmt-22{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:163.9pt;left:264.04pt;z-index:80;letter-spacing:.002em;"} Logical Instruction
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:240.94pt;left:264.04pt;z-index:125;letter-spacing:.001em;"} No meaning
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.98pt;left:264.04pt;z-index:236;letter-spacing:.002em;"} Result is all zeroes
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:375.7pt;left:264.04pt;z-index:297;letter-spacing:.001em;"} After Shift operation
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:395.02pt;left:264.04pt;z-index:360;letter-spacing:.001em;"} 1 was left in carry flag
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:433.54pt;left:264.04pt;z-index:378;letter-spacing:.001em;"} No meaning
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:257.32pt;z-index:56;letter-spacing:-.001em;"} niversity Program - V1.0
%span.fmt-1{:style => "white-space:pre;"}
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%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:491.32pt;z-index:498;letter-spacing:.001em;"} lags
%img{:alt => "__rendered_path__482", :src => "./target/5511e5966c47a9e3f1b1532f12f3331c.png", :style => "position:absolute;left:251.14pt;top:158.56pt;width:1.1pt;height:313pt;z-index:482;"}/
%span.fmt-22{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:163.9pt;left:490.48pt;z-index:102;letter-spacing:.001em;"} Arithmetic Instruction
%img{:alt => "__rendered_path__483", :src => "./target/83977022fe0906c888bc1623f33f2f05.png", :style => "position:absolute;left:478.66pt;top:160.7pt;width:1.1pt;height:312.9pt;z-index:483;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:240.94pt;left:490.48pt;z-index:158;letter-spacing:.002em;"} Bit 31 of the result has been set
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:260.14pt;left:490.48pt;z-index:195;letter-spacing:.001em;"} Indicates a negative number in
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:279.46pt;left:490.48pt;z-index:212;letter-spacing:.001em;"} signed operations
%img{:alt => "__rendered_path__59", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:59;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.98pt;left:490.48pt;z-index:264;letter-spacing:.001em;"} Result of operation was zero
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:375.7pt;left:490.48pt;z-index:328;letter-spacing:.001em;"} Result was greater than 32 bits
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:433.54pt;left:490.48pt;z-index:409;letter-spacing:.001em;"} Result was greater than 31 bits
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:452.74pt;left:490.48pt;z-index:450;letter-spacing:.001em;"} Indicates a possible corruption of
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:472.06pt;left:490.48pt;z-index:473;letter-spacing:.002em;"} the sign bit in signed
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:491.26pt;left:490.48pt;z-index:480;"} numbers
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__58", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:58;"}/
%img{:alt => "Image_84_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:60;"}/
%img{:alt => "__rendered_path__499", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:499;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:766.12pt;z-index:57;"} 8
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 9
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-25{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3619pt;left:169.12pt;z-index:550;letter-spacing:.001em;"} The Program Counter (R15)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.4396pt;z-index:106;letter-spacing:-.001em;"}
%span.fmt-24 *
When the processor is executing in ARM state:
%span.fmt-24{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:145;letter-spacing:-.003em;"} • All instructions are 32 bits in length
%span.fmt-24{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:183;letter-spacing:-.003em;"} • All instructions must be word aligned
%span.fmt-24{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:257;letter-spacing:-.002em;"} • Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to
%span.fmt-24{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:262.65pt;left:156.88pt;z-index:314;"} zero (as instruction cannot be halfword or byte aligned).
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.33pt;left:98.4403pt;z-index:386;"}
%span.fmt-24 *
R14 is used as the subroutine link register (LR) and stores the return
%img{:alt => "__rendered_path__59", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:59;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:312.81pt;left:122.68pt;z-index:442;"} address when Branch with Link operations are performed,
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:334.29pt;left:122.68pt;z-index:465;"} calculated from the PC.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:362.97pt;left:98.4393pt;z-index:501;"}
%span.fmt-24 *
Thus to return from a linked branch
%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:390.33pt;left:137.32pt;z-index:513;letter-spacing:.002em;"}
%span.fmt-24 •
MOV r15,r14
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:420.33pt;left:122.68pt;z-index:515;letter-spacing:.001em;"} or
%img{:alt => "__rendered_path__551", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:551;"}/
%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:447.69pt;left:137.32pt;z-index:525;letter-spacing:.002em;"}
%span.fmt-24 •
MOV pc,lr
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__58", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:58;"}/
%img{:alt => "Image_94_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:60;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:57;"} RM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:766.12pt;z-index:57;"} 9
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 10
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-31{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3621pt;left:510.88pt;z-index:520;letter-spacing:.001em;"} d
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.2419pt;left:511.96pt;z-index:540;letter-spacing:.001em;"} T
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.2419pt;left:591.76pt;z-index:544;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
%span.fmt-27{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:181.17pt;left:79.9596pt;z-index:62;"} *
%span.fmt-27{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:460.17pt;left:79.9603pt;z-index:412;"} *
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:8;letter-spacing:.003em;"} The A
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3621pt;left:241.36pt;z-index:519;letter-spacing:.001em;"} Exception Han
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.2419pt;left:231.52pt;z-index:539;letter-spacing:.001em;"} and the Vector
%span.fmt-28{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:181.17pt;left:104.2pt;z-index:97;"}
When an exception occurs,
%span.fmt-29 t
%span.fmt-29 h
%span.fmt-29 e
%span.fmt-29
%span.fmt-29 c
%span.fmt-29 o
%span.fmt-29 r
%span.fmt-29 e
%span.fmt-29 :
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:204.55pt;left:118.84pt;z-index:126;letter-spacing:-.001em;"}
%span.fmt-30 •
Copies CPSR into SPSR_&lt;mode&gt;
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:230.23pt;left:118.84pt;z-index:154;letter-spacing:-.002em;"}
%span.fmt-30 •
Sets appropriate CPSR bits
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:260.62pt;left:177.16pt;z-index:201;letter-spacing:.001em;"} If core implements ARM Architecture 4T and is
%img{:alt => "__rendered_path__155", :src => "./target/4e0d8c4b36630c41663f1cbdd157e8b1.png", :style => "position:absolute;left:159.2pt;top:270.48pt;width:6pt;height:3pt;z-index:155;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:279.82pt;left:177.16pt;z-index:231;letter-spacing:.001em;"} currently in Thumb state, then
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:305.5pt;left:211.12pt;z-index:253;letter-spacing:.002em;"} ARM state is entered.
%img{:alt => "__rendered_path__232", :src => "./target/837bcc38d27afc917ea051f691a69882.png", :style => "position:absolute;left:198.4pt;top:313.54pt;width:6pt;height:6pt;z-index:232;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:331.18pt;left:177.16pt;z-index:269;letter-spacing:.001em;"} Mode field bits
%img{:alt => "__rendered_path__155", :src => "./target/4e0d8c4b36630c41663f1cbdd157e8b1.png", :style => "position:absolute;left:159.2pt;top:341.04pt;width:6pt;height:3pt;z-index:155;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:356.86pt;left:177.16pt;z-index:308;letter-spacing:.001em;"} Interrupt disable flags if appropriate.
%img{:alt => "__rendered_path__155", :src => "./target/4e0d8c4b36630c41663f1cbdd157e8b1.png", :style => "position:absolute;left:159.2pt;top:366.72pt;width:6pt;height:3pt;z-index:155;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:377.83pt;left:118.84pt;z-index:345;letter-spacing:-.002em;"}
%span.fmt-30 •
Maps in appropriate banked registers
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:403.51pt;left:118.84pt;z-index:385;letter-spacing:-.001em;"}
%span.fmt-30 •
Stores the “
%span.fmt-32 r
%span.fmt-32 e
%span.fmt-32 t
%span.fmt-32 u
%span.fmt-32 r
%span.fmt-32 n
%span.fmt-32
%span.fmt-32 a
%span.fmt-32 d
%span.fmt-32 d
%span.fmt-32 r
%span.fmt-32 e
%span.fmt-32 s
= succeed "\u201D" do
%span.fmt-32 s
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:429.19pt;left:118.84pt;z-index:411;letter-spacing:-.003em;"}
%span.fmt-30 •
Sets PC to vector address
%span.fmt-28{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:460.17pt;left:104.2pt;z-index:450;"} To return, exception handler needs to:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:488.26pt;left:118.84pt;z-index:480;letter-spacing:.002em;"} • Restore CPSR from SPSR_&lt;mode&gt;
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:513.94pt;left:118.84pt;z-index:506;letter-spacing:.002em;"} • Restore PC from LR_&lt;mode&gt;
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:102.64pt;z-index:56;"} M Instruction Set - ARM University Program - V1.0
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3621pt;left:534.52pt;z-index:524;letter-spacing:.002em;"} ling
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.2419pt;left:535.6pt;z-index:543;letter-spacing:.002em;"} abl
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:199.93pt;left:533.8pt;z-index:560;letter-spacing:.005em;"} 0x00000000
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:226.21pt;left:533.8pt;z-index:630;letter-spacing:.005em;"} 0x00000004
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:252.37pt;left:533.8pt;z-index:620;letter-spacing:.005em;"} 0x00000008
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:278.65pt;left:531.88pt;z-index:610;letter-spacing:.005em;"} 0x0000000C
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:304.93pt;left:533.8pt;z-index:600;letter-spacing:.005em;"} 0x00000010
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:330.97pt;left:533.8pt;z-index:590;letter-spacing:.005em;"} 0x00000014
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:357.25pt;left:533.8pt;z-index:580;letter-spacing:.005em;"} 0x00000018
%span.fmt-33{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:383.53pt;left:531.88pt;z-index:570;letter-spacing:.005em;"} 0x0000001C
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%img{:alt => "__rendered_path__546", :src => "./target/0151658f2ef97efa3e4b02eac7451bb2.png", :style => "position:absolute;left:599.91pt;top:191.77pt;width:140.8pt;height:27.2pt;z-index:546;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:195.32pt;left:655.24pt;z-index:635;letter-spacing:-.001em;"} Reset
%img{:alt => "__rendered_path__545", :src => "./target/19f44841ffa7793f4df8862f6bd58176.png", :style => "position:absolute;left:600.4pt;top:191.48pt;width:140pt;height:27pt;z-index:545;"}/
%img{:alt => "__rendered_path__548", :src => "./target/15b61529fcea6931fe3f105142fa9621.png", :style => "position:absolute;left:599.91pt;top:217.07pt;width:140.8pt;height:27.1pt;z-index:548;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:222.43pt;left:606.76pt;z-index:656;letter-spacing:-.001em;"} Undefined Instruction
%img{:alt => "__rendered_path__547", :src => "./target/efc255b2874dd1e7c073783e0b77cb9a.png", :style => "position:absolute;left:600.4pt;top:216.68pt;width:140pt;height:27pt;z-index:547;"}/
%img{:alt => "__rendered_path__546", :src => "./target/0151658f2ef97efa3e4b02eac7451bb2.png", :style => "position:absolute;left:599.91pt;top:243.25pt;width:140.8pt;height:27.2pt;z-index:546;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:248.72pt;left:615.52pt;z-index:712;"} Software Interrupt
%img{:alt => "__rendered_path__545", :src => "./target/19f44841ffa7793f4df8862f6bd58176.png", :style => "position:absolute;left:600.4pt;top:242.96pt;width:140pt;height:27pt;z-index:545;"}/
%img{:alt => "__rendered_path__546", :src => "./target/0151658f2ef97efa3e4b02eac7451bb2.png", :style => "position:absolute;left:599.91pt;top:269.53pt;width:140.8pt;height:27.2pt;z-index:546;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:275pt;left:627.16pt;z-index:694;letter-spacing:-.001em;"} Prefetch Abort
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "__rendered_path__545", :src => "./target/19f44841ffa7793f4df8862f6bd58176.png", :style => "position:absolute;left:600.4pt;top:269.24pt;width:140pt;height:27pt;z-index:545;"}/
%img{:alt => "__rendered_path__546", :src => "./target/0151658f2ef97efa3e4b02eac7451bb2.png", :style => "position:absolute;left:599.91pt;top:295.81pt;width:140.8pt;height:27.2pt;z-index:546;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:301.28pt;left:637.72pt;z-index:680;letter-spacing:.001em;"} Data Abort
%img{:alt => "__rendered_path__545", :src => "./target/19f44841ffa7793f4df8862f6bd58176.png", :style => "position:absolute;left:600.4pt;top:295.52pt;width:140pt;height:27pt;z-index:545;"}/
%img{:alt => "__rendered_path__548", :src => "./target/15b61529fcea6931fe3f105142fa9621.png", :style => "position:absolute;left:599.91pt;top:321.95pt;width:140.8pt;height:27.1pt;z-index:548;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.32pt;left:643.6pt;z-index:670;letter-spacing:-.001em;"} Reserved
%img{:alt => "__rendered_path__547", :src => "./target/efc255b2874dd1e7c073783e0b77cb9a.png", :style => "position:absolute;left:600.4pt;top:321.56pt;width:140pt;height:27pt;z-index:547;"}/
%img{:alt => "__rendered_path__546", :src => "./target/0151658f2ef97efa3e4b02eac7451bb2.png", :style => "position:absolute;left:599.91pt;top:348.13pt;width:140.8pt;height:27.2pt;z-index:546;"}/
%span.fmt-34{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:353.6pt;left:658.12pt;z-index:662;"} IRQ
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%div{:style => "position:absolute;top:70.3622pt;left:202.6pt;z-index:85;letter-spacing:.001em;"} The Instruction Pipeline
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%div{:style => "position:absolute;top:153.57pt;left:131.8pt;z-index:156;"} The ARM uses a pipeline in order to increase the speed of the flow of
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%div{:style => "position:absolute;top:175.05pt;left:131.8pt;z-index:186;"} instructions to the processor.
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%div{:style => "position:absolute;top:203.73pt;left:147.52pt;z-index:258;letter-spacing:-.002em;"} • Allows several operations to be undertaken simultaneously, rather than
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%div{:style => "position:absolute;top:425.04pt;left:695.32pt;z-index:501;"} k
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%div{:style => "position:absolute;top:461.52pt;left:435.04pt;z-index:563;"} Write register(s) back to Register Bank
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%div{:style => "position:absolute;top:483.57pt;left:131.8pt;z-index:328;letter-spacing:.001em;"} Rather than pointing to the instruction being executed, the
%img{:alt => "Image_121_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
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%div{:style => "position:absolute;top:505.05pt;left:131.8pt;z-index:371;letter-spacing:.001em;"} PC points to the instruction being fetched.
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:58;letter-spacing:-.001em;"} struction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:277pt;z-index:76;letter-spacing:.001em;"} Quiz #1 - Verbal
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What registers are used to store the program counter and link register?
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%span.fmt-38 *
What is r13 often used to store?
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%span.fmt-38 *
Which mode, or modes has the fewest available number of registers
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%div{:style => "position:absolute;top:348.69pt;left:122.68pt;z-index:276;"} available? How many and why?
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:50.5622pt;left:165.4pt;z-index:82;letter-spacing:.001em;"} ARM Instruction Set F
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%div{:style => "position:absolute;top:127.34pt;left:119.32pt;z-index:1321;letter-spacing:.023em;"} 2827
%div{:style => "position:absolute;top:127.34pt;left:308.08pt;z-index:1321;letter-spacing:.021em;"} 1615
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%div{:style => "position:absolute;top:127.34pt;left:559.6pt;z-index:1321;"} 0
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%div{:style => "position:absolute;top:152.3pt;left:80.7996pt;z-index:520;letter-spacing:.003em;"} Cond 0 0 I Opcode S Rn Rd Operand2
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%div{:style => "position:absolute;top:178.46pt;left:80.7994pt;z-index:583;letter-spacing:.003em;"} Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm
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%div{:style => "position:absolute;top:204.74pt;left:80.7996pt;z-index:836;letter-spacing:.003em;"} Cond 0 0 0 0 1 U A S RdHi RdLo Rs 1 0 0 1 Rm
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%img{:alt => "__rendered_path__445", :src => "./target/5c5c1ce14e75b2c5e5c67ede216b9d6e.png", :style => "position:absolute;left:226.6pt;top:170.4pt;width:15pt;height:26pt;z-index:445;"}/
%img{:alt => "__rendered_path__451", :src => "./target/722fa05319136ae54c5ddaa19fa307e4.png", :style => "position:absolute;left:69.2796pt;top:144.12pt;width:62pt;height:26pt;z-index:451;"}/
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%div{:style => "position:absolute;top:230.78pt;left:80.6796pt;z-index:659;letter-spacing:.003em;"} Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm
%img{:alt => "__rendered_path__447", :src => "./target/1649358bc253aeaca71d7a7bdd39da9b.png", :style => "position:absolute;left:132.16pt;top:170.4pt;width:94pt;height:26pt;z-index:447;"}/
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%div{:style => "position:absolute;top:256.94pt;left:80.6784pt;z-index:715;letter-spacing:.003em;"} Cond 0 1 I P U B W L Rn Rd Offset
%img{:alt => "__rendered_path__455", :src => "./target/fa8e149a1a790a395f6583a25668d6c7.png", :style => "position:absolute;left:320.92pt;top:144.12pt;width:62pt;height:26pt;z-index:455;"}/
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%div{:style => "position:absolute;top:283.1pt;left:80.6781pt;z-index:771;letter-spacing:.003em;"} Cond 1 0 0 P U S W L Rn Register List
%img{:alt => "__rendered_path__455", :src => "./target/fa8e149a1a790a395f6583a25668d6c7.png", :style => "position:absolute;left:258.04pt;top:144.12pt;width:62pt;height:26pt;z-index:455;"}/
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%div{:style => "position:absolute;top:309.38pt;left:81.1596pt;z-index:902;letter-spacing:.003em;"} Cond 0 0 0 P U 1 W L Rn Rd Offset1 1 S H 1 Offset2
%img{:alt => "__rendered_path__451", :src => "./target/722fa05319136ae54c5ddaa19fa307e4.png", :style => "position:absolute;left:179.32pt;top:144.12pt;width:62pt;height:26pt;z-index:451;"}/
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%div{:style => "position:absolute;top:335.06pt;left:80.0796pt;z-index:1308;letter-spacing:.003em;"} Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm
%img{:alt => "__rendered_path__460", :src => "./target/857c0fbee08bd967c4533d8f5d442ac4.png", :style => "position:absolute;left:69.2796pt;top:170.4pt;width:62pt;height:26pt;z-index:460;"}/
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%div{:style => "position:absolute;top:361.34pt;left:81.3996pt;z-index:949;letter-spacing:.003em;"} Cond 1 0 1 L Offset
%img{:alt => "__rendered_path__462", :src => "./target/c3ddf753c37e10ceacdecf8eda0ea51a.png", :style => "position:absolute;left:320.92pt;top:170.4pt;width:62pt;height:26pt;z-index:462;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:387.38pt;left:82.7197pt;z-index:1247;letter-spacing:.003em;"} Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn
%img{:alt => "__rendered_path__462", :src => "./target/c3ddf753c37e10ceacdecf8eda0ea51a.png", :style => "position:absolute;left:258.04pt;top:170.4pt;width:62pt;height:26pt;z-index:462;"}/
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%div{:style => "position:absolute;top:413.9pt;left:81.3996pt;z-index:1015;letter-spacing:.003em;"} Cond 1 1 0 P U N W L Rn CRd CPNum Offset
%img{:alt => "__rendered_path__462", :src => "./target/c3ddf753c37e10ceacdecf8eda0ea51a.png", :style => "position:absolute;left:383.8pt;top:170.4pt;width:62pt;height:26pt;z-index:462;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:440.18pt;left:81.3995pt;z-index:1078;letter-spacing:.003em;"} Cond 1 1 1 0 Op1 CRn CRd CPNum Op2 0 CRm
%img{:alt => "__rendered_path__462", :src => "./target/c3ddf753c37e10ceacdecf8eda0ea51a.png", :style => "position:absolute;left:446.68pt;top:170.4pt;width:62pt;height:26pt;z-index:462;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:466.34pt;left:81.3981pt;z-index:1141;letter-spacing:.003em;"} Cond 1 1 1 0 Op1 L CRn Rd CPNum Op2 1 CRm
%img{:alt => "__rendered_path__445", :src => "./target/5c5c1ce14e75b2c5e5c67ede216b9d6e.png", :style => "position:absolute;left:210.88pt;top:222.84pt;width:15pt;height:26pt;z-index:445;"}/
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%div{:style => "position:absolute;top:492.5pt;left:81.3968pt;z-index:1185;letter-spacing:.003em;"} Cond 1 1 1 1 SWI Number
%img{:alt => "__rendered_path__584", :src => "./target/4838108ea271899961ab6cd348e47296.png", :style => "position:absolute;left:163.6pt;top:249pt;width:15pt;height:26pt;z-index:584;"}/
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:50.5622pt;left:594.4pt;z-index:87;letter-spacing:.001em;"} rmat
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%div{:style => "position:absolute;top:125.63pt;left:583.48pt;z-index:103;letter-spacing:.001em;"} Instruction type
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%div{:style => "position:absolute;top:153.84pt;left:583.48pt;z-index:134;letter-spacing:.002em;"} Data processing / PSR Transfer
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%span.fmt-41 L
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%span.fmt-41{:style => "white-space:pre;"}
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Halfword transfer : Immediate offset
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Halfword transfer: Register offset
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%span.fmt-41{:style => "white-space:pre;"}
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Branch Exchange
%span.fmt-42 (
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%span.fmt-42 T
%span.fmt-42
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%span.fmt-41{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:410.04pt;left:583.48pt;z-index:369;letter-spacing:.002em;"} Coprocessor data transfer
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%span.fmt-41{:style => "white-space:pre;"}
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%div{:style => "position:absolute;top:461.64pt;left:583.48pt;z-index:424;letter-spacing:.002em;"} Coprocessor register transfer
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%b Page 14
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%div{:style => "position:absolute;top:70.3622pt;left:217.72pt;z-index:82;letter-spacing:.001em;"} Conditional Execution
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%span.fmt-47 *
Most instruction sets only allow branches to be executed conditionally.
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%span.fmt-47 *
However by reusing the condition evaluation hardware, ARM effectively
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%div{:style => "position:absolute;top:205.17pt;left:122.68pt;z-index:259;"} increases number of instructions.
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:332;letter-spacing:-.002em;"} • All instructions contain a condition field which determines whether the
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%div{:style => "position:absolute;top:255.45pt;left:156.76pt;z-index:355;letter-spacing:-.001em;"} CPU will execute them.
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%div{:style => "position:absolute;top:284.13pt;left:137.32pt;z-index:398;letter-spacing:-.003em;"} • Non-executed instructions soak up 1 cycle.
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%div{:style => "position:absolute;top:312.81pt;left:176.2pt;z-index:469;letter-spacing:-.001em;"} Still have to complete cycle so as to allow fetching and decoding of
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%div{:style => "position:absolute;top:334.29pt;left:195.64pt;z-index:492;"} following instructions.
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This removes the need for many branches, which stall the pipeline (3
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%div{:style => "position:absolute;top:413.13pt;left:137.32pt;z-index:630;letter-spacing:-.003em;"} • Allows very dense in-line code, without branches.
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%div{:style => "position:absolute;top:441.81pt;left:137.32pt;z-index:701;letter-spacing:-.002em;"} • The Time penalty of not executing several conditional instructions is
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%div{:style => "position:absolute;top:463.29pt;left:156.76pt;z-index:745;"} frequently less than overhead of the branch
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:54.0422pt;left:319.6pt;z-index:67;"} C
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%div{:style => "position:absolute;top:180.45pt;left:202.12pt;z-index:104;letter-spacing:.001em;"} Cond
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%div{:style => "position:absolute;top:252.59pt;left:105.64pt;z-index:128;"} 0000 = EQ - Z set (equal)
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%div{:style => "position:absolute;top:277.91pt;left:105.64pt;z-index:158;"} 0001 = NE - Z clear (not equal)
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%div{:style => "position:absolute;top:303.23pt;left:105.64pt;z-index:191;"} 0010 = HS / CS - C set (unsigned
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%div{:style => "position:absolute;top:320.03pt;left:154.6pt;z-index:206;"} higher or same)
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%div{:style => "position:absolute;top:345.23pt;left:105.64pt;z-index:240;"} 0011 = LO / CC - C clear (unsigned
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%div{:style => "position:absolute;top:387.35pt;left:105.64pt;z-index:273;"} 0100 = MI -N set (negative)
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%div{:style => "position:absolute;top:412.55pt;left:105.64pt;z-index:305;"} 0101 = PL - N clear (positive or
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%div{:style => "position:absolute;top:429.35pt;left:154.6pt;z-index:310;letter-spacing:.001em;"} zero)
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%div{:style => "position:absolute;top:454.67pt;left:105.64pt;z-index:338;letter-spacing:.001em;"} 0110 = VS - V set (overflow)
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%div{:style => "position:absolute;top:479.99pt;left:105.64pt;z-index:370;"} 0111 = VC - V clear (no overflow)
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%div{:style => "position:absolute;top:505.19pt;left:105.64pt;z-index:399;"} 1000 = HI - C set and Z clear
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%div{:style => "position:absolute;top:521.99pt;left:154.6pt;z-index:416;"} (unsigned higher)
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:46;"} The ARM Instruction Set - ARM University Pro
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%div{:style => "position:absolute;top:552.8pt;left:364.12pt;z-index:52;"} -
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%div{:style => "position:absolute;top:54.0422pt;left:476.92pt;z-index:81;letter-spacing:.001em;"} n Field
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%div{:style => "position:absolute;top:250.67pt;left:474.28pt;z-index:454;"} 1001 = LS - C clear or Z (set unsigned
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%div{:style => "position:absolute;top:267.71pt;left:523.24pt;z-index:469;"} lower or same)
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%div{:style => "position:absolute;top:293.27pt;left:474.28pt;z-index:508;letter-spacing:.001em;"} 1010 = GE - N set and V set, or N clear
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%div{:style => "position:absolute;top:310.31pt;left:523.24pt;z-index:527;"} and V clear (&gt;or =)
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%div{:style => "position:absolute;top:335.87pt;left:474.28pt;z-index:568;"} 1011 = LT - N set and V clear, or N clear
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%div{:style => "position:absolute;top:352.91pt;left:523.24pt;z-index:581;letter-spacing:.001em;"} and V set (&gt;)
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%div{:style => "position:absolute;top:378.47pt;left:474.28pt;z-index:622;"} 1100 = GT - Z clear, and either N set and
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%div{:style => "position:absolute;top:395.51pt;left:523.24pt;z-index:653;letter-spacing:.001em;"} V set, or N clear and V set (&gt;)
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%div{:style => "position:absolute;top:420.95pt;left:474.28pt;z-index:695;"} 1101 = LE - Z set, or N set and V clear,or
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%div{:style => "position:absolute;top:437.99pt;left:523.24pt;z-index:722;letter-spacing:.001em;"} N clear and V set (&lt;, or =)
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%div{:style => "position:absolute;top:463.55pt;left:474.28pt;z-index:739;"} 1110 = AL - always
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%div{:style => "position:absolute;top:489.11pt;left:474.28pt;z-index:759;letter-spacing:.001em;"} 1111 = NV - reserved.
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%div{:style => "position:absolute;top:552.8pt;left:116.68pt;z-index:12;letter-spacing:.001em;"} I
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%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:100;"} *
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%div{:style => "position:absolute;top:341.49pt;left:98.4427pt;z-index:376;"} *
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:11;letter-spacing:-.001em;"} The ARM
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%div{:style => "position:absolute;top:49.3622pt;left:206.8pt;z-index:84;letter-spacing:.001em;"} Using and updating the
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:281.32pt;z-index:99;letter-spacing:.001em;"} Condition Field
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:122.68pt;z-index:168;letter-spacing:.001em;"} To execute an instruction conditionally, simply postfix it with the
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:190;letter-spacing:.001em;"} appropriate condition:
%span.fmt-52{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:237;letter-spacing:-.003em;"} • For example an add instruction takes the form:
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%div{:style => "position:absolute;top:232.65pt;left:176.2pt;z-index:272;letter-spacing:-.01em;"}
%span.fmt-52
ADD r0,r1,r2
%div{:style => "position:absolute;top:232.65pt;left:409.24pt;z-index:272;letter-spacing:-.001em;"} ; r0 = r1 + r2 (ADDAL)
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%div{:style => "position:absolute;top:262.65pt;left:137.32pt;z-index:318;letter-spacing:-.003em;"} • To execute this only if the zero flag is set:
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%div{:style => "position:absolute;top:290.13pt;left:176.2pt;z-index:357;letter-spacing:-.005em;"}
%span.fmt-52
ADDEQ r0,r1,r2 ; If zero flag set then
%span.fmt-52 …
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:312.65pt;left:409.24pt;z-index:375;letter-spacing:-.001em;"} ; ... r0 = r1 + r2
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%div{:style => "position:absolute;top:341.49pt;left:122.68pt;z-index:449;letter-spacing:.001em;"} By default, data processing operations do not affect the condition flags
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%div{:style => "position:absolute;top:362.97pt;left:122.68pt;z-index:522;"} (apart from the comparisons where this is the only effect). To cause the
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%div{:style => "position:absolute;top:384.45pt;left:122.68pt;z-index:598;letter-spacing:.001em;"} condition flags to be updated, the S bit of the instruction needs to be set
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%div{:style => "position:absolute;top:405.93pt;left:122.68pt;z-index:665;letter-spacing:.001em;"} by postfixing the instruction (and any condition code) with an “S”.
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%div{:style => "position:absolute;top:434.61pt;left:137.32pt;z-index:725;letter-spacing:-.002em;"} • For example to add two numbers and set the condition flags:
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%div{:style => "position:absolute;top:462.09pt;left:176.2pt;z-index:754;letter-spacing:-.009em;"}
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ADDS r0,r1,r2
%div{:style => "position:absolute;top:462.09pt;left:409.24pt;z-index:754;letter-spacing:-.001em;"} ; r0 = r1 + r2
%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:484.61pt;left:409.24pt;z-index:773;letter-spacing:-.001em;"} ; ... and set flags
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%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:58;letter-spacing:-.001em;"} nstruction Set - ARM University Program - V1.0
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%b Page 17
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:552.8pt;left:102.64pt;z-index:10;"} M
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%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:13;letter-spacing:.001em;"} n
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
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%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:12;"} I
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
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%div{:style => "position:absolute;top:70.3622pt;left:209.92pt;z-index:545;letter-spacing:.001em;"} Branch instructions (1)
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%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:153.33pt;left:143.32pt;z-index:85;letter-spacing:.008em;"}
%span.fmt-54 *
%span.fmt-55 B
%span.fmt-55 r
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%div{:style => "position:absolute;top:153.33pt;left:378.76pt;z-index:85;letter-spacing:-.001em;"} B{&lt;cond&gt;} label
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%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:182.01pt;left:143.32pt;z-index:132;letter-spacing:.005em;"}
%span.fmt-54 *
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%div{:style => "position:absolute;top:182.01pt;left:378.76pt;z-index:132;letter-spacing:-.001em;"} BL{&lt;cond&gt;} sub_routine_label
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%div{:style => "position:absolute;top:230.54pt;left:144.52pt;z-index:706;letter-spacing:.003em;"} 31
%div{:style => "position:absolute;top:230.54pt;left:197.68pt;z-index:706;letter-spacing:.011em;"} 28 27
%div{:style => "position:absolute;top:230.54pt;left:248.56pt;z-index:706;letter-spacing:-.001em;"} 25 24 23
%div{:style => "position:absolute;top:230.54pt;left:679.96pt;z-index:706;"} 0
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%div{:style => "position:absolute;top:256.81pt;left:157.24pt;z-index:644;letter-spacing:-.001em;"} Cond 1 0 1 L
%div{:style => "position:absolute;top:256.81pt;left:446.32pt;z-index:644;"} Offset
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0 = Branch
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%div{:style => "position:absolute;top:304.55pt;left:405.28pt;z-index:699;"} 1 = Branch with link
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%div{:style => "position:absolute;top:322.89pt;left:327.64pt;z-index:659;letter-spacing:.001em;"} Condition field
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%span.fmt-55{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.41pt;left:143.32pt;z-index:199;letter-spacing:.002em;"}
%span.fmt-54 *
The offset for branch instructions is calculated by the assembler:
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:384.09pt;left:182.68pt;z-index:264;letter-spacing:-.1em;"} •
%div{:style => "position:absolute;top:384.09pt;left:211.96pt;z-index:264;"} By taking the difference between the branch instruction and the
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:405.57pt;left:211.96pt;z-index:315;"} target address minus 8 (to allow for the pipeline).
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:434.25pt;left:182.68pt;z-index:380;letter-spacing:-.1em;"} •
%div{:style => "position:absolute;top:434.25pt;left:211.96pt;z-index:380;"} This gives a 26 bit offset which is right shifted 2 bits (as the
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%div{:style => "position:absolute;top:455.73pt;left:211.96pt;z-index:438;letter-spacing:.001em;"} bottom two bits are always zero as instructions are word
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%div{:style => "position:absolute;top:477.21pt;left:211.96pt;z-index:488;"} aligned) and stored into the instruction encoding.
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:505.89pt;left:182.68pt;z-index:522;letter-spacing:-.1em;"} •
%div{:style => "position:absolute;top:505.89pt;left:211.96pt;z-index:522;"} This gives a range of 32 Mbytes.
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:58;letter-spacing:-.001em;"} struction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:209.92pt;z-index:84;letter-spacing:.001em;"} Branch instructions (2)
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%span.fmt-59 *
When executing the instruction, the processor:
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:210;letter-spacing:-.002em;"} • shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
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%span.fmt-59 *
Execution then continues from the new PC, once the pipeline has been
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%div{:style => "position:absolute;top:233.97pt;left:122.68pt;z-index:289;"} refilled.
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%span.fmt-59 *
The "Branch with link" instruction implements a subroutine call by
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%div{:style => "position:absolute;top:284.13pt;left:122.68pt;z-index:403;"} writing PC-4 into the LR of the current bank.
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%div{:style => "position:absolute;top:312.81pt;left:137.32pt;z-index:476;letter-spacing:-.002em;"} • i.e. the address of the next instruction following the branch with link
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%div{:style => "position:absolute;top:334.29pt;left:156.76pt;z-index:504;"} (allowing for the pipeline).
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%span.fmt-59 *
To return from subroutine, simply need to restore the PC from the LR:
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%span.fmt-59 •
MOV pc, lr
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%div{:style => "position:absolute;top:420.33pt;left:137.32pt;z-index:643;letter-spacing:-.002em;"} • Again, pipeline has to refill before execution continues.
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%span.fmt-59 *
The "Branch" instruction does not affect LR.
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%span.fmt-59 *
Note: Architecture 4T offers a further ARM branch instruction, BX
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%div{:style => "position:absolute;top:506.49pt;left:137.32pt;z-index:800;letter-spacing:-.003em;"} • See Thumb Instruction Set Module for details.
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%div{:style => "position:absolute;top:70.3622pt;left:154.96pt;z-index:89;letter-spacing:.001em;"} Data processing Instructions
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%span.fmt-61 *
Largest family of ARM instructions, all sharing the same instructio
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:166;"} format.
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%span.fmt-61 *
Contains:
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:198;letter-spacing:-.005em;"} • Arithmetic operations
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%div{:style => "position:absolute;top:262.65pt;left:137.32pt;z-index:250;letter-spacing:-.002em;"} • Comparisons (no results - just set condition codes)
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:269;letter-spacing:-.006em;"} • Logical operations
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%div{:style => "position:absolute;top:320.01pt;left:137.32pt;z-index:301;letter-spacing:-.004em;"} • Data movement between registers
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%span.fmt-61 *
Remember, this is a load / store architecture
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• These instruction only work on registers,
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%span.fmt-63 O
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memory.
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%span.fmt-61 *
They each perform a specific operation on one or two operands.
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%div{:style => "position:absolute;top:434.73pt;left:137.32pt;z-index:500;letter-spacing:-.003em;"} • First operand always a register - Rn
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%div{:style => "position:absolute;top:463.41pt;left:137.32pt;z-index:551;letter-spacing:-.003em;"} • Second operand sent to the ALU via barrel shifter.
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%span.fmt-61 *
We will examine the barrel shifter shortly.
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%div{:style => "position:absolute;top:70.3622pt;left:218.68pt;z-index:76;letter-spacing:.001em;"} Arithmetic Oper
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Operations are:
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:121;letter-spacing:-.017em;"} • ADD
%div{:style => "position:absolute;top:183.69pt;left:253.84pt;z-index:121;"} operand1 + operand2
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%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:152;letter-spacing:-.017em;"} • ADC
%div{:style => "position:absolute;top:212.49pt;left:253.84pt;z-index:152;"} operand1 + operand2 + carry
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%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:174;letter-spacing:-.018em;"} • SUB
%div{:style => "position:absolute;top:241.17pt;left:253.84pt;z-index:174;"} operand1 - operand2
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%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:208;letter-spacing:-.017em;"} • SBC
%div{:style => "position:absolute;top:269.85pt;left:253.84pt;z-index:208;"} operand1 - operand2 + carry -1
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%div{:style => "position:absolute;top:298.53pt;left:137.32pt;z-index:230;letter-spacing:-.017em;"} • RSB
%div{:style => "position:absolute;top:298.53pt;left:253.84pt;z-index:230;"} operand2 - operand1
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%div{:style => "position:absolute;top:327.21pt;left:137.32pt;z-index:263;letter-spacing:-.017em;"} • RSC
%div{:style => "position:absolute;top:327.21pt;left:253.84pt;z-index:263;"} operand2 - operand1 + carry - 1
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Syntax:
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%div{:style => "position:absolute;top:384.57pt;left:137.32pt;z-index:311;letter-spacing:-.003em;"} • &lt;Operation&gt;{&lt;cond&gt;}{S} Rd, Rn, Operand2
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Examples
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%div{:style => "position:absolute;top:441.93pt;left:137.32pt;z-index:335;letter-spacing:-.006em;"} • ADD r0, r1, r2
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%div{:style => "position:absolute;top:470.73pt;left:137.32pt;z-index:352;letter-spacing:-.006em;"} • SUBGT r3, r3, #1
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%div{:style => "position:absolute;top:499.41pt;left:137.32pt;z-index:370;letter-spacing:-.005em;"} • RSBLES r4, r5, #5
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%div{:style => "position:absolute;top:183.69pt;left:639.16pt;z-index:164;"} S
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%div{:style => "position:absolute;top:183.69pt;left:655.24pt;z-index:166;"} b
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%div{:style => "position:absolute;top:183.69pt;left:670.72pt;z-index:168;letter-spacing:.001em;"} t
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:298.48pt;z-index:72;letter-spacing:.001em;"} Comparisons
%span.fmt-67{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:113;"}
%span.fmt-66 *
The only effect of the comparisons is to
%span.fmt-63{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:163;letter-spacing:-.002em;"}
%span.fmt-66 •
UPDATE THE CONDITION FLAGS.
%span.fmt-66 T
%span.fmt-66 h
%span.fmt-66 u
%span.fmt-66 s
%span.fmt-66
%span.fmt-66 n
%span.fmt-66 o
%span.fmt-66
%span.fmt-66 n
%span.fmt-66 e
%span.fmt-66 e
%span.fmt-66 d
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%span.fmt-66 t
%span.fmt-66 o
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%span.fmt-66 s
%span.fmt-66 e
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%span.fmt-66
%img{:alt => "__rendered_path__141", :src => "./target/eefb386a08b9fac6298b24be3d86ae7c.png", :style => "position:absolute;left:156.76pt;top:202.76pt;width:313pt;height:3pt;z-index:141;"}/
%span.fmt-67{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:98.4401pt;z-index:185;letter-spacing:-.002em;"}
%span.fmt-66 *
Operations are:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:231;letter-spacing:-.017em;"} • CMP
%div{:style => "position:absolute;top:241.17pt;left:253.84pt;z-index:231;"} operand1 - operand2, but result not written
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:278;letter-spacing:-.017em;"} • CMN
%div{:style => "position:absolute;top:269.85pt;left:253.84pt;z-index:278;"} operand1 + operand2, but result not written
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:298.53pt;left:137.32pt;z-index:327;letter-spacing:-.017em;"} • TST
%div{:style => "position:absolute;top:298.53pt;left:253.84pt;z-index:327;"} operand1 AND operand2, but result not written
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.21pt;left:137.32pt;z-index:376;letter-spacing:-.018em;"} • TEQ
%div{:style => "position:absolute;top:327.21pt;left:253.84pt;z-index:376;"} operand1 EOR operand2, but result not written
%span.fmt-67{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:98.4438pt;z-index:384;letter-spacing:-.002em;"}
%span.fmt-66 *
Syntax:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:384.57pt;left:137.32pt;z-index:417;letter-spacing:-.003em;"} • &lt;Operation&gt;{&lt;cond&gt;} Rn, Operand2
%span.fmt-67{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:413.25pt;left:98.443pt;z-index:427;letter-spacing:-.002em;"}
%span.fmt-66 *
Examples:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:441.93pt;left:137.32pt;z-index:437;letter-spacing:-.017em;"} • CMP
%div{:style => "position:absolute;top:441.93pt;left:253.84pt;z-index:437;"} r0, r1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:470.73pt;left:137.32pt;z-index:449;letter-spacing:-.013em;"} • TSTEQ
%div{:style => "position:absolute;top:470.73pt;left:253.84pt;z-index:449;letter-spacing:.001em;"} r2, #5
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
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%div{:style => "position:absolute;top:183.69pt;left:650.2pt;z-index:165;"}
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:665.2pt;z-index:167;letter-spacing:.001em;"} i
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:676.12pt;z-index:169;"} .
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "Image_229_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__450", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:450;"}/
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%b Page 22
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
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%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
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%div{:style => "position:absolute;top:70.3622pt;left:246.64pt;z-index:79;letter-spacing:.001em;"} Logical Operations
%span.fmt-69{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:95;letter-spacing:-.002em;"}
%span.fmt-68 *
Operations are:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:120;letter-spacing:-.017em;"} • AND
%div{:style => "position:absolute;top:183.69pt;left:253.84pt;z-index:120;"} operand1 AND operand2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:145;letter-spacing:-.018em;"} • EOR
%div{:style => "position:absolute;top:212.49pt;left:253.84pt;z-index:145;"} operand1 EOR operand2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:169;letter-spacing:-.017em;"} • ORR
%div{:style => "position:absolute;top:241.17pt;left:253.84pt;z-index:169;"} operand1 OR operand2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:213;letter-spacing:-.017em;"} • BIC
%div{:style => "position:absolute;top:269.85pt;left:253.84pt;z-index:213;"} operand1 AND NOT operand2 [ie bit clear]
%span.fmt-69{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:298.53pt;left:98.4426pt;z-index:221;letter-spacing:-.002em;"}
%span.fmt-68 *
Syntax:
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.21pt;left:137.32pt;z-index:261;letter-spacing:-.003em;"} • &lt;Operation&gt;{&lt;cond&gt;}{S} Rd, Rn, Operand2
%span.fmt-69{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:98.4427pt;z-index:271;letter-spacing:-.002em;"}
%span.fmt-68 *
Examples:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:384.57pt;left:137.32pt;z-index:285;letter-spacing:-.017em;"} • AND
%div{:style => "position:absolute;top:384.57pt;left:253.84pt;z-index:285;letter-spacing:.001em;"} r0, r1, r2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:413.25pt;left:137.32pt;z-index:301;letter-spacing:-.014em;"} • BICEQ
%div{:style => "position:absolute;top:413.25pt;left:253.84pt;z-index:301;letter-spacing:.001em;"} r2, r3, #7
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:441.93pt;left:137.32pt;z-index:314;letter-spacing:-.015em;"} • EORS
%div{:style => "position:absolute;top:441.93pt;left:253.84pt;z-index:314;"} r1,r3,r0
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "Image_239_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__315", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:315;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%b Page 23
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-70{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:473.32pt;z-index:71;"} m
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:529.36pt;z-index:73;letter-spacing:.001em;"} n
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:278.92pt;z-index:70;letter-spacing:.001em;"} Data Move
%span.fmt-71{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.4391pt;z-index:90;letter-spacing:-.002em;"}
%span.fmt-70 *
Operations are:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:102;letter-spacing:-.017em;"} • MOV
%div{:style => "position:absolute;top:183.69pt;left:253.84pt;z-index:102;"} operand2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:118;letter-spacing:-.017em;"} • MVN
%div{:style => "position:absolute;top:212.49pt;left:253.84pt;z-index:118;letter-spacing:.001em;"} NOT operand2
%span.fmt-71{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:122.68pt;z-index:158;letter-spacing:.001em;"} Note that these make no use of operand1.
%span.fmt-71{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:98.4393pt;z-index:166;letter-spacing:-.002em;"}
%span.fmt-70 *
Syntax:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:298.53pt;left:137.32pt;z-index:202;letter-spacing:-.003em;"} • &lt;Operation&gt;{&lt;cond&gt;}{S} Rd, Operand2
%span.fmt-71{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.21pt;left:98.4386pt;z-index:212;letter-spacing:-.002em;"}
%span.fmt-70 *
Examples:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:137.32pt;z-index:222;letter-spacing:-.017em;"} • MOV
%div{:style => "position:absolute;top:355.89pt;left:253.84pt;z-index:222;"} r0, r1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:384.57pt;left:137.32pt;z-index:234;letter-spacing:-.015em;"} • MOVS
%div{:style => "position:absolute;top:384.57pt;left:253.84pt;z-index:234;letter-spacing:.001em;"} r2, #10
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:413.25pt;left:137.32pt;z-index:245;letter-spacing:-.013em;"} • MVNEQ
%div{:style => "position:absolute;top:413.25pt;left:253.84pt;z-index:245;"} r1,#0
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:507.76pt;z-index:72;"} e
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:553pt;z-index:74;"} t
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
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%img{:alt => "Image_249_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__246", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:246;"}/
%span.fmt-0{:style => "white-space:pre;"}
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%b Page 24
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-74{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:448.24pt;z-index:67;"} #
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:301.96pt;z-index:42;"} y
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:312.4pt;z-index:44;letter-spacing:.001em;"} P
%img{:alt => "__rendered_path__143", :src => "./target/00ddb66eaafb5cd71cad19414d99c1ab.png", :style => "position:absolute;left:64.3596pt;top:213.96pt;width:9pt;height:14pt;z-index:143;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%img{:alt => "__rendered_path__141", :src => "./target/a450beae758d72e90185dce9587b8059.png", :style => "position:absolute;left:66.3996pt;top:506.12pt;width:14pt;height:9pt;z-index:141;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:378pt;left:163.96pt;z-index:158;"} Yes
%img{:alt => "__rendered_path__135", :src => "./target/a40e3ab31f044c09621ce74ed171681c.png", :style => "position:absolute;left:156.16pt;top:417.4pt;width:13pt;height:13pt;z-index:135;"}/
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:440.71pt;left:105.88pt;z-index:118;letter-spacing:.001em;"} r0 = r0 - r1
%img{:alt => "__rendered_path__105", :src => "./target/ad7eb9cb4c46b8e134b8457b270b4d87.png", :style => "position:absolute;left:102.4pt;top:436.4pt;width:109pt;height:39pt;z-index:105;"}/
%img{:alt => "__rendered_path__106", :src => "./target/408898fa44b818043175a8f0ff45e4fb.png", :style => "position:absolute;left:96.0396pt;top:430.16pt;width:109pt;height:39pt;z-index:106;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:28;letter-spacing:.001em;"} RM Instruction Set -
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%div{:style => "position:absolute;top:163.99pt;left:238.84pt;z-index:76;"} Start
%img{:alt => "__rendered_path__132", :src => "./target/e634a7f436cee227a3a2c034039142af.png", :style => "position:absolute;left:256.12pt;top:230.16pt;width:9pt;height:14pt;z-index:132;"}/
%img{:alt => "__rendered_path__145", :src => "./target/ce3a717688e12fdf459b94df25b295ea.png", :style => "position:absolute;left:249.16pt;top:210.56pt;width:14pt;height:9pt;z-index:145;"}/
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:259.03pt;left:232pt;z-index:92;letter-spacing:.001em;"} r0 = r1
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:279.55pt;left:254.8pt;z-index:93;letter-spacing:.001em;"} ?
%img{:alt => "__rendered_path__83", :src => "./target/10955c6d5d14227513717ac9082f3afa.png", :style => "position:absolute;left:211.24pt;top:249.12pt;width:112pt;height:62pt;z-index:83;"}/
%img{:alt => "__rendered_path__84", :src => "./target/dbb6c0565e9f27d57c99373748221c71.png", :style => "position:absolute;left:204.88pt;top:242.88pt;width:112pt;height:62pt;z-index:84;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:315.12pt;left:271.6pt;z-index:161;letter-spacing:.002em;"} No
%img{:alt => "__rendered_path__132", :src => "./target/e634a7f436cee227a3a2c034039142af.png", :style => "position:absolute;left:256.12pt;top:338.64pt;width:9pt;height:14pt;z-index:132;"}/
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:369.19pt;left:232pt;z-index:103;letter-spacing:.001em;"} r0 &gt; r1
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:389.59pt;left:254.8pt;z-index:104;letter-spacing:.001em;"} ?
%img{:alt => "__rendered_path__94", :src => "./target/47ec8ecceac2bea718138be514c6d80c.png", :style => "position:absolute;left:211.24pt;top:360.16pt;width:112pt;height:61pt;z-index:94;"}/
%img{:alt => "__rendered_path__95", :src => "./target/8a4f7b75eae2482ede97e1f59d9d27d1.png", :style => "position:absolute;left:204.88pt;top:352.92pt;width:112pt;height:62pt;z-index:95;"}/
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%div{:style => "position:absolute;top:552.8pt;left:216.28pt;z-index:41;letter-spacing:-.002em;"} ARM Universit
%img{:alt => "__rendered_path__69", :src => "./target/1ba4ff9f62c0b3a4999eadaf503a63e7.png", :style => "position:absolute;left:223.24pt;top:159.52pt;width:87pt;height:43pt;z-index:69;"}/
%img{:alt => "__rendered_path__70", :src => "./target/c38dfef99e1afab9d745401fa863389d.png", :style => "position:absolute;left:217.12pt;top:153.4pt;width:87pt;height:43pt;z-index:70;"}/
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%div{:style => "position:absolute;top:552.8pt;left:308.92pt;z-index:43;letter-spacing:.001em;"}
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%div{:style => "position:absolute;top:70.3622pt;left:353.44pt;z-index:66;letter-spacing:.001em;"} Quiz
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%div{:style => "position:absolute;top:254.88pt;left:323.44pt;z-index:151;"} Yes
%div{:style => "position:absolute;top:254.88pt;left:413.08pt;z-index:151;letter-spacing:.001em;"}
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%img{:alt => "__rendered_path__147", :src => "./target/dc84a4364ebd5c27b636a9b93f8e7301.png", :style => "position:absolute;left:377.2pt;top:268.76pt;width:14pt;height:9pt;z-index:147;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:378pt;left:332.92pt;z-index:154;letter-spacing:.002em;"} No
%img{:alt => "__rendered_path__137", :src => "./target/10f5fbc623120037a3a9783f74c0a980.png", :style => "position:absolute;left:357.88pt;top:418.4pt;width:13pt;height:12pt;z-index:137;"}/
%span.fmt-72{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:440.71pt;left:326.8pt;z-index:130;letter-spacing:.001em;"} r1 = r1 - r0
%img{:alt => "__rendered_path__119", :src => "./target/5e8d786c1b81b63fa9e0f65e635c9e92.png", :style => "position:absolute;left:323.2pt;top:436.4pt;width:110pt;height:39pt;z-index:119;"}/
%img{:alt => "__rendered_path__106", :src => "./target/408898fa44b818043175a8f0ff45e4fb.png", :style => "position:absolute;left:316.96pt;top:430.16pt;width:109pt;height:39pt;z-index:106;"}/
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%div{:style => "position:absolute;top:552.8pt;left:320.8pt;z-index:56;letter-spacing:-.001em;"} rogram - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:469.84pt;z-index:68;"} 2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:180.57pt;left:503.68pt;z-index:162;"} *
%img{:alt => "__rendered_path__77", :src => "./target/c07d04e27a6fd9532f2985efff0133b2.png", :style => "position:absolute;left:397pt;top:256.08pt;width:87pt;height:44pt;z-index:77;"}/
%img{:alt => "__rendered_path__70", :src => "./target/c38dfef99e1afab9d745401fa863389d.png", :style => "position:absolute;left:390.88pt;top:250.84pt;width:87pt;height:43pt;z-index:70;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:445.77pt;left:503.68pt;z-index:361;"} *
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
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%div{:style => "position:absolute;top:180.57pt;left:527.92pt;z-index:178;"} Convert the GCD
%img{:alt => "__rendered_path__78", :src => "./target/02e9fa8f89b01a5e49bc7caf537d9705.png", :style => "position:absolute;left:390.34pt;top:250.28pt;width:88.1pt;height:44.1pt;z-index:78;"}/
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%div{:style => "position:absolute;top:202.05pt;left:527.92pt;z-index:202;"} algorithm given in this
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%div{:style => "position:absolute;top:223.53pt;left:527.92pt;z-index:216;"} flowchart into
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:252.21pt;left:542.56pt;z-index:236;letter-spacing:-.005em;"} 1) “Normal” assembler,
%img{:alt => "__rendered_path__107", :src => "./target/c7abd8eb096c9c23792df8a0527a153a.png", :style => "position:absolute;left:95.5pt;top:430.3pt;width:110.1pt;height:39.4pt;z-index:107;"}/
%img{:alt => "__rendered_path__134", :src => "./target/54e27bb034b30e05652f57a0588e4ee6.png", :style => "position:absolute;left:161.91pt;top:383.51pt;width:44.1pt;height:41.4pt;z-index:134;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:273.81pt;left:562pt;z-index:260;"} where only branches can
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%img{:alt => "__rendered_path__136", :src => "./target/f52991a2694049fccfb595deedf75020.png", :style => "position:absolute;left:316.85pt;top:384.29pt;width:47.8pt;height:41pt;z-index:136;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:295.29pt;left:562pt;z-index:275;"} be conditional.
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "__rendered_path__138", :src => "./target/60f129f54c6ce3cbf574225582f44dd5.png", :style => "position:absolute;left:149.26pt;top:469.62pt;width:1.1pt;height:32.3pt;z-index:138;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:323.97pt;left:542.56pt;z-index:298;letter-spacing:-.005em;"} 2) ARM assembler, where
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%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:345.45pt;left:562pt;z-index:319;"} all instructions are
%img{:alt => "__rendered_path__140", :src => "./target/35a93b0c216ac498d46be36c60d14c61.png", :style => "position:absolute;left:75.04pt;top:510pt;width:294.9pt;height:1.1pt;z-index:140;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:366.93pt;left:562pt;z-index:337;"} conditional, thus
%img{:alt => "__rendered_path__142", :src => "./target/2ba3880522b47bd845126fd114f69f46.png", :style => "position:absolute;left:68.26pt;top:223.36pt;width:1.1pt;height:287.2pt;z-index:142;"}/
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%div{:style => "position:absolute;top:388.41pt;left:562pt;z-index:360;"} improving code density.
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%div{:style => "position:absolute;top:445.77pt;left:527.92pt;z-index:387;"} The only instructions you
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%div{:style => "position:absolute;top:467.25pt;left:527.92pt;z-index:411;"} need are CMP, B and SUB.
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%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 24
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%b Page 25
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:16;letter-spacing:-.001em;"} str
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%div{:style => "position:absolute;top:552.8pt;left:151.72pt;z-index:20;letter-spacing:-.001em;"} cti
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%div{:style => "position:absolute;top:70.3622pt;left:173.56pt;z-index:84;letter-spacing:.001em;"} Quiz #2 - Sample Solutio
%span.fmt-76{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:159.45pt;left:196.12pt;z-index:104;"} “Normal” Assembler
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%div{:style => "position:absolute;top:207.24pt;left:196.12pt;z-index:145;"} gcd cmp r0, r1 ;reached the end?
%img{:alt => "__rendered_path__105", :src => "./target/2a8b7698247fce9323c10cb450a0234f.png", :style => "position:absolute;left:281.32pt;top:178.52pt;width:95pt;height:3pt;z-index:105;"}/
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%div{:style => "position:absolute;top:228.36pt;left:257.44pt;z-index:162;"} beq stop
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:249.48pt;left:257.44pt;z-index:189;"} blt less ;if r0 &gt; r1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:270.48pt;left:257.44pt;z-index:226;"} sub r0, r0, r1 ;subtract r1 from r0
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.6pt;left:257.44pt;z-index:233;letter-spacing:.001em;"} bal gcd
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:312.72pt;left:196.12pt;z-index:277;"} less sub r1, r1, r0 ;subtract r0 from r1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:333.84pt;left:257.44pt;z-index:284;letter-spacing:.001em;"} bal gcd
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:354.84pt;left:196.12pt;z-index:288;letter-spacing:-.001em;"} stop
%span.fmt-76{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:399.09pt;left:196.12pt;z-index:313;letter-spacing:.001em;"} ARM Conditional Assembler
%img{:alt => "__rendered_path__292", :src => "./target/2835fab57415b56fa4bccc540c1a4c26.png", :style => "position:absolute;left:196.12pt;top:418.16pt;width:48pt;height:3pt;z-index:292;"}/
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%div{:style => "position:absolute;top:446.88pt;left:196.12pt;z-index:350;"} gcd cmp r0, r1 ;if r0 &gt; r1
%img{:alt => "__rendered_path__304", :src => "./target/56371823c0017a930e87762bd0ed1b56.png", :style => "position:absolute;left:248.8pt;top:418.16pt;width:101pt;height:3pt;z-index:304;"}/
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%div{:style => "position:absolute;top:468pt;left:257.44pt;z-index:388;"} subgt r0, r0, r1 ;subtract r1 from r0
%img{:alt => "__rendered_path__314", :src => "./target/e60d758f8a487a9fcad2fa5b64406bcd.png", :style => "position:absolute;left:354.52pt;top:418.16pt;width:90pt;height:3pt;z-index:314;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:489.12pt;left:257.44pt;z-index:432;"} sublt r1, r1, r0 ;else subtract r0 from r1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:510.12pt;left:257.44pt;z-index:467;"} bne gcd ;reached the end?
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%div{:style => "position:absolute;top:552.8pt;left:174.16pt;z-index:56;letter-spacing:-.001em;"} n Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:259.6pt;z-index:79;letter-spacing:.001em;"} The Barrel Shifter
%span{:style => "white-space:pre;"}
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%span.fmt-78 *
The ARM doesnt have actual shift instructions.
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%span.fmt-78 *
Instead it has a barrel shifter which provides a mechanism to carry out
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:233.97pt;left:122.68pt;z-index:237;"} shifts as part of other instructions.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.33pt;left:98.4391pt;z-index:289;"}
%span.fmt-78 *
So what operations does the barrel shifter support?
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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.fmt-81{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
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%div{:style => "position:absolute;top:70.3622pt;left:198.16pt;z-index:182;letter-spacing:.001em;"} Barrel Shifter - Left Shift
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.4396pt;z-index:133;"}
%span.fmt-80 *
Shifts left by the specified amount (multiplies by powers of two) e.g.
%span.fmt-80{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:176.2pt;z-index:156;letter-spacing:.001em;"} LSL #5 = multiply by 32
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:333.69pt;left:315.52pt;z-index:206;"} Logical Shift Left (LSL)
%span.fmt-82{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:412.41pt;left:192.04pt;z-index:225;letter-spacing:.001em;"}
%span.fmt-81 C
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3621pt;left:173.44pt;z-index:350;letter-spacing:.001em;"} Barrel Shifter - Right Shifts
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%div{:style => "position:absolute;top:157.77pt;left:90.3996pt;z-index:81;"} Logical Shift Right
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%div{:style => "position:absolute;top:172.77pt;left:452.32pt;z-index:404;"} Logical Shift Right
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%div{:style => "position:absolute;top:186.33pt;left:90.3996pt;z-index:103;letter-spacing:-.007em;"}
%span.fmt-85 •
Shifts right by the
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%div{:style => "position:absolute;top:250.77pt;left:98.6795pt;z-index:152;letter-spacing:.001em;"} two) e.g.
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%div{:style => "position:absolute;top:282.09pt;left:98.6795pt;z-index:173;letter-spacing:.001em;"} LSR #5 = divide by 32
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%div{:style => "position:absolute;top:344.49pt;left:90.3994pt;z-index:426;letter-spacing:.001em;"} Arithmetic Shift Right
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%span{:style => "position:relative;left:0pt;top:-1pt;"} c
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%span{:style => "position:relative;left:0pt;top:-1pt;"} S
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%span{:style => "position:relative;left:0pt;top:-1pt;"} R
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%div{:style => "position:absolute;top:373.05pt;left:90.3996pt;z-index:222;letter-spacing:-.006em;"}
%span.fmt-85 •
Shifts right (divides by
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%div{:style => "position:absolute;top:437.49pt;left:98.6794pt;z-index:284;"} for 2's complement
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%div{:style => "position:absolute;top:458.97pt;left:98.6793pt;z-index:450;"} operations. e.g.
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%span{:style => "position:relative;left:0pt;top:4pt;"} d
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%div{:style => "position:absolute;top:490.29pt;left:98.6793pt;z-index:322;letter-spacing:.001em;"} ASR #5 = divide by 32
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%b Page 29
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%div{:style => "position:absolute;top:70.3622pt;left:192.76pt;z-index:85;letter-spacing:.001em;"} Barrel Shifter - Rotation
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%div{:style => "position:absolute;top:130.65pt;left:79.5991pt;z-index:418;letter-spacing:.001em;"} Rotate Right (ROR)
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%div{:style => "position:absolute;top:161.85pt;left:79.5996pt;z-index:133;letter-spacing:-.003em;"} • Similar to an ASR but the
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%div{:style => "position:absolute;top:224.73pt;left:89.4387pt;z-index:194;letter-spacing:.001em;"} the MSB.
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%div{:style => "position:absolute;top:255.93pt;left:89.4387pt;z-index:205;"} e.g. ROR #5
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%span.fmt-88 •
Note the last bit rotated is
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%div{:style => "position:absolute;top:308.01pt;left:89.4397pt;z-index:262;"} also used as the Carry Out.
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%div{:style => "position:absolute;top:370.41pt;left:79.5996pt;z-index:289;letter-spacing:.001em;"} Rotate Right Extended (RRX)
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%div{:style => "position:absolute;top:387.57pt;left:401.56pt;z-index:464;letter-spacing:.001em;"} Rotate Right through Carry
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%div{:style => "position:absolute;top:401.61pt;left:79.5996pt;z-index:315;"} • This operation uses the
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%div{:style => "position:absolute;top:422.61pt;left:89.4395pt;z-index:342;letter-spacing:.001em;"} CPSR C flag as a 33rd bit.
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%div{:style => "position:absolute;top:453.81pt;left:79.6006pt;z-index:430;letter-spacing:-.004em;"}
%span.fmt-88 •
Rotates right by 1 bit.
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%div{:style => "position:absolute;top:474.69pt;left:89.4405pt;z-index:385;letter-spacing:.001em;"} Encoded as ROR #0.
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:197.49pt;left:672.64pt;z-index:400;letter-spacing:.001em;"} CF
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:12;letter-spacing:-.001em;"} The ARM I
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%div{:style => "position:absolute;top:251.47pt;left:261.4pt;z-index:431;letter-spacing:.001em;"} Barrel
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%div{:style => "position:absolute;top:278.59pt;left:257.92pt;z-index:438;"} Shifter
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%div{:style => "position:absolute;top:396.07pt;left:199.36pt;z-index:424;"} ALU
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%div{:style => "position:absolute;top:502.63pt;left:187.12pt;z-index:413;"} Result
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%div{:style => "position:absolute;top:552.8pt;left:181.84pt;z-index:56;letter-spacing:-.001em;"} Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:49.3622pt;left:488.32pt;z-index:86;letter-spacing:.001em;"} l Shifter:
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%div{:style => "position:absolute;top:91.242pt;left:488.32pt;z-index:104;letter-spacing:.001em;"} perand
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%div{:style => "position:absolute;top:144.57pt;left:490.12pt;z-index:281;letter-spacing:.001em;"} Register, optionally with shift
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%div{:style => "position:absolute;top:164.97pt;left:490.12pt;z-index:299;letter-spacing:.001em;"} operation applied.
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%div{:style => "position:absolute;top:192.33pt;left:490.12pt;z-index:329;letter-spacing:.001em;"} Shift value can be either be:
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%div{:style => "position:absolute;top:219.57pt;left:504.76pt;z-index:352;letter-spacing:-.001em;"} • 5 bit unsigned integer
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%div{:style => "position:absolute;top:246.81pt;left:504.76pt;z-index:381;letter-spacing:-.001em;"} • Specified in bottom byte of
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%div{:style => "position:absolute;top:267.21pt;left:524.2pt;z-index:398;letter-spacing:.001em;"} another register.
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%div{:style => "position:absolute;top:309.33pt;left:491.8pt;z-index:121;letter-spacing:.001em;"} Immediate value
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%div{:style => "position:absolute;top:336.57pt;left:506.44pt;z-index:134;letter-spacing:-.004em;"} • 8 bit number
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%div{:style => "position:absolute;top:363.81pt;left:506.44pt;z-index:164;letter-spacing:-.001em;"} • Can be rotated right through
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%div{:style => "position:absolute;top:384.21pt;left:525.88pt;z-index:182;letter-spacing:.001em;"} an even number of
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%div{:style => "position:absolute;top:431.97pt;left:506.44pt;z-index:218;letter-spacing:-.001em;"} • Assembler will calculate
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%div{:style => "position:absolute;top:452.37pt;left:525.88pt;z-index:238;letter-spacing:.001em;"} rotate for you from
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%div{:style => "position:absolute;top:472.77pt;left:525.88pt;z-index:247;letter-spacing:.002em;"} constant.
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%div{:style => "position:absolute;top:49.3622pt;left:255.4pt;z-index:77;letter-spacing:.001em;"} Second Operand :
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%div{:style => "position:absolute;top:91.242pt;left:273.64pt;z-index:93;letter-spacing:.001em;"} Shifted Register
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%div{:style => "position:absolute;top:160.29pt;left:124pt;z-index:160;"}
%span.fmt-93 *
The amount by which the register is to be shifted is contained in
%span.fmt-94{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:181.77pt;left:148.24pt;z-index:170;"} either:
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%div{:style => "position:absolute;top:210.45pt;left:162.88pt;z-index:226;letter-spacing:-.002em;"} • the immediate 5-bit field in the instruction
%span.fmt-95{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:239.13pt;left:201.76pt;z-index:239;letter-spacing:-.001em;"}
%span.fmt-93
NO OVERHEAD
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%div{:style => "position:absolute;top:267.81pt;left:201.76pt;z-index:290;letter-spacing:-.001em;"} Shift is done for free - executes in single cycle.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:296.49pt;left:162.88pt;z-index:329;letter-spacing:-.003em;"} • the bottom byte of a register (not PC)
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
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%div{:style => "position:absolute;top:325.29pt;left:201.76pt;z-index:363;letter-spacing:-.001em;"} Then takes extra cycle to execute
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%div{:style => "position:absolute;top:353.97pt;left:201.76pt;z-index:422;letter-spacing:-.005em;"} ARM doesn t have enough read ports to read 3 registers at
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%div{:style => "position:absolute;top:375.45pt;left:221.2pt;z-index:427;"} once.
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%div{:style => "position:absolute;top:404.13pt;left:201.76pt;z-index:475;letter-spacing:-.001em;"} Then same as on other processors where shift is
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:425.61pt;left:221.2pt;z-index:496;letter-spacing:-.001em;"} separate instruction.
%img{:alt => "__rendered_path__618", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:618;"}/
%span.fmt-94{:style => "white-space:pre;"}
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%span.fmt-93 *
If no shift is specified then a default shift is applied: LSL #0
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%div{:style => "position:absolute;top:482.97pt;left:162.88pt;z-index:617;letter-spacing:-.002em;"} • i.e. barrel shifter has no effect on value in register.
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%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:58;"} Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:226.77pt;left:729.28pt;z-index:358;"} n
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%div{:style => "position:absolute;top:276.93pt;left:728.68pt;z-index:474;"} n
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%div{:style => "position:absolute;top:552.8pt;left:116.68pt;z-index:12;letter-spacing:.001em;"} I
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%div{:style => "position:absolute;top:155.01pt;left:98.439pt;z-index:102;"} *
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%div{:style => "position:absolute;top:226.77pt;left:98.4388pt;z-index:290;"} *
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%div{:style => "position:absolute;top:327.09pt;left:98.4387pt;z-index:486;"} *
%span.fmt-96{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:405.93pt;left:98.4381pt;z-index:558;"} *
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:11;letter-spacing:-.001em;"} The ARM
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:255.4pt;z-index:77;letter-spacing:.001em;"} Second Operand :
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%div{:style => "position:absolute;top:91.242pt;left:198.16pt;z-index:101;letter-spacing:.001em;"} Using a Shifted Register
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%div{:style => "position:absolute;top:155.01pt;left:122.68pt;z-index:175;letter-spacing:.001em;"} Using a multiplication instruction to multiply by a constant means first
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:241;letter-spacing:.001em;"} loading the constant into a register and then waiting a number of
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%div{:style => "position:absolute;top:197.97pt;left:122.68pt;z-index:289;"} internal cycles for the instruction to complete.
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%div{:style => "position:absolute;top:226.77pt;left:122.68pt;z-index:357;letter-spacing:.001em;"} A more optimum solution can often be found by using some combinatio
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%div{:style => "position:absolute;top:248.25pt;left:122.68pt;z-index:400;letter-spacing:.001em;"} of MOVs, ADDs, SUBs and RSBs with shifts.
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%div{:style => "position:absolute;top:276.93pt;left:137.32pt;z-index:473;letter-spacing:-.002em;"} • Multiplications by a constant equal to a ((power of 2) 1) can be done i
%img{:alt => "__rendered_path__457", :src => "./target/c80b41e8294f83f36063c1372cc0d8e4.png", :style => "position:absolute;left:586.79pt;top:279.47pt;width:10pt;height:15pt;z-index:457;"}/
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%div{:style => "position:absolute;top:298.41pt;left:156.76pt;z-index:485;letter-spacing:-.001em;"} one cycle.
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%div{:style => "position:absolute;top:327.09pt;left:122.68pt;z-index:506;letter-spacing:.001em;"} Example: r0 = r1 * 5
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%div{:style => "position:absolute;top:377.73pt;left:253.84pt;z-index:557;"} ï ADD r0, r1, r1, LSL #2
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%div{:style => "position:absolute;top:405.93pt;left:122.68pt;z-index:580;letter-spacing:.001em;"} Example: r2 = r3 * 105
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%div{:style => "position:absolute;top:470.85pt;left:253.84pt;z-index:677;"} ï RSB r2, r3, r3, LSL #4
%div{:style => "position:absolute;top:470.85pt;left:487pt;z-index:677;"} ; r2 = r3 * 15
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%div{:style => "position:absolute;top:492.33pt;left:253.84pt;z-index:713;"} ï RSB r2, r2, r2, LSL #3
%div{:style => "position:absolute;top:492.33pt;left:487pt;z-index:713;"} ; r2 = r2 * 7
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%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:56;letter-spacing:-.001em;"} nstruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:155.01pt;left:724.72pt;z-index:170;"} n
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
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%div{:style => "position:absolute;top:49.3622pt;left:255.4pt;z-index:77;letter-spacing:.001em;"} Second Operand :
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%div{:style => "position:absolute;top:91.242pt;left:240.28pt;z-index:96;letter-spacing:.001em;"} Immediate Value (1)
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%div{:style => "position:absolute;top:155.01pt;left:98.4389pt;z-index:169;"}
%span.fmt-98 *
There is no single instruction which will load a 32 bit immediate consta
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:231;"} into a register without performing a data load from memory.
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%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:269;letter-spacing:-.003em;"} • All ARM instructions are 32 bits long
%span.fmt-98{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:329;letter-spacing:-.002em;"} • ARM instructions do not use the instruction stream as data.
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%div{:style => "position:absolute;top:262.65pt;left:98.4373pt;z-index:394;"}
%span.fmt-98 *
The data processing instruction format has 12 bits available for
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:284.13pt;left:122.68pt;z-index:402;"} operand2
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%div{:style => "position:absolute;top:312.81pt;left:137.32pt;z-index:457;letter-spacing:-.002em;"} • If used directly this would only give a range of 4096.
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%div{:style => "position:absolute;top:341.49pt;left:98.4365pt;z-index:527;"}
%span.fmt-98 *
Instead it is used to store 8 bit constants, giving a range of 0 - 255.
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%div{:style => "position:absolute;top:370.17pt;left:98.4369pt;z-index:592;"}
%span.fmt-98 *
These 8 bits can then be rotated right through an even number of
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%div{:style => "position:absolute;top:391.65pt;left:122.68pt;z-index:628;"} positions (ie RORs by 0, 2, 4,..30).
%span.fmt-98{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:420.33pt;left:137.32pt;z-index:701;letter-spacing:-.002em;"} • This gives a much larger range of constants that can be directly loaded,
%span.fmt-98{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:441.81pt;left:156.76pt;z-index:752;"} though some constants will still need to be loaded
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%div{:style => "position:absolute;top:463.29pt;left:156.76pt;z-index:764;"} from memory.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:116.68pt;z-index:12;letter-spacing:.001em;"} I
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%div{:style => "position:absolute;top:155.01pt;left:98.4389pt;z-index:97;"} *
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%div{:style => "position:absolute;top:292.77pt;left:98.4381pt;z-index:317;"} *
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%div{:style => "position:absolute;top:350.13pt;left:98.4408pt;z-index:408;"} *
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%div{:style => "position:absolute;top:428.97pt;left:98.439pt;z-index:568;"} *
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%div{:style => "position:absolute;top:486.45pt;left:98.4397pt;z-index:668;"} *
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:11;letter-spacing:-.001em;"} The ARM
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%div{:style => "position:absolute;top:49.3622pt;left:255.4pt;z-index:77;letter-spacing:.001em;"} Second Operand :
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:240.28pt;z-index:96;letter-spacing:.001em;"} Immediate Value (2)
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%div{:style => "position:absolute;top:155.01pt;left:122.68pt;z-index:111;"} This gives us:
%span.fmt-102{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.45pt;left:137.32pt;z-index:127;letter-spacing:-.006em;"} • 0 - 255
%div{:style => "position:absolute;top:183.45pt;left:409.24pt;z-index:127;letter-spacing:.001em;"} [0 - 0xff]
%span.fmt-102{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:210.81pt;left:137.32pt;z-index:186;letter-spacing:-.002em;"} • 256,260,264,..,1020
%div{:style => "position:absolute;top:210.81pt;left:409.24pt;z-index:186;letter-spacing:.001em;"} [0x100-0x3fc, step 4, 0x40-0xff ror 30]
%span.fmt-102{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:238.05pt;left:137.32pt;z-index:249;letter-spacing:-.002em;"} • 1024,1040,1056,..,4080
%div{:style => "position:absolute;top:238.05pt;left:409.24pt;z-index:249;letter-spacing:.001em;"} [0x400-0xff0, step 16, 0x40-0xff ror 28]
%span.fmt-102{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:265.29pt;left:137.32pt;z-index:314;letter-spacing:-.002em;"} • 4096,4160, 4224,..,16320
%div{:style => "position:absolute;top:265.29pt;left:409.24pt;z-index:314;letter-spacing:.001em;"} [0x1000-0x3fc0, step 64, 0x40-0xff ror 2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:292.77pt;left:122.68pt;z-index:356;"} These can be loaded using, for example:
%span.fmt-100{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:321.45pt;left:137.32pt;z-index:407;letter-spacing:-.005em;"} • MOV r0, #0x40, 26
%div{:style => "position:absolute;top:321.45pt;left:409.24pt;z-index:407;"} ; =&gt; MOV r0, #0x1000 (ie 4096)
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:350.13pt;left:122.68pt;z-index:478;"} To make this easier, the assembler will convert to this form for us if
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:371.61pt;left:122.68pt;z-index:513;"} simply given the required constant:
%span.fmt-100{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:400.29pt;left:137.32pt;z-index:565;letter-spacing:-.007em;"} • MOV r0, #4096
%div{:style => "position:absolute;top:400.29pt;left:409.24pt;z-index:565;"} ; =&gt; MOV r0, #0x1000 (ie 0x40 ror 2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:428.97pt;left:122.68pt;z-index:621;"} The bitwise complements can also be formed using MVN:
%span.fmt-100{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:457.65pt;left:137.32pt;z-index:667;letter-spacing:-.004em;"} • MOV r0, #0xFFFFFFFF
%div{:style => "position:absolute;top:457.65pt;left:409.24pt;z-index:667;"} ; assembles to MVN r0, #0
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:486.45pt;left:122.68pt;z-index:728;"} If the required constant cannot be generated, an error will
%img{:alt => "Image_365_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:507.93pt;left:122.68pt;z-index:740;"} be reported.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:56;letter-spacing:-.001em;"} nstruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
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%span.fmt-102{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:265.29pt;left:729.52pt;z-index:316;"} ]
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span.fmt-100{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:400.29pt;left:733.96pt;z-index:567;"} )
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%span.fmt-0{:style => "white-space:pre;"}
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.fmt-104{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
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%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:159.28pt;z-index:90;letter-spacing:.001em;"} Loading full 32 bit constants
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.439pt;z-index:159;"}
%span.fmt-103 *
Although the MOV/MVN mechansim will load a large range of constants
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:232;"} into a register, sometimes this mechansim will not generate the required
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:197.97pt;left:122.68pt;z-index:241;"} constant.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:226.77pt;left:98.4386pt;z-index:312;"}
%span.fmt-103 *
Therefore, the assembler also provides a method which will load
%span.fmt-63 A
%span.fmt-63 N
%span.fmt-63 Y
32
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:248.25pt;left:122.68pt;z-index:325;letter-spacing:.001em;"} bit constant:
%span.fmt-26{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:275.61pt;left:137.32pt;z-index:350;"}
%span.fmt-103 •
LDR rd,=numeric constant
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:305.61pt;left:98.4384pt;z-index:422;"}
%span.fmt-103 *
If the constant can be constructed using either a MOV or MVN then this
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.09pt;left:122.68pt;z-index:465;"} will be the instruction actually generated.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.77pt;left:98.4384pt;z-index:533;"}
%span.fmt-103 *
Otherwise, the assembler will produce an LDR instruction with a PC-
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:377.25pt;left:122.68pt;z-index:591;"} relative address to read the constant from a literal pool.
%span.fmt-106{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:403.43pt;left:137.32pt;z-index:628;letter-spacing:-.021em;"}
%span.fmt-105 •
LDR r0,=0x42
%div{:style => "position:absolute;top:403.43pt;left:331.6pt;z-index:628;"} ; generates MOV r0,#0x42
%span.fmt-106{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:426.11pt;left:137.32pt;z-index:689;letter-spacing:-.009em;"}
%span.fmt-105 •
LDR r0,=0x55555555 ; generate LDR r0,[pc, offset to lit pool]
%img{:alt => "__rendered_path__816", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:816;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:451.29pt;left:98.4393pt;z-index:762;"}
%span.fmt-103 *
As this mechanism will always generate the best instruction for a given
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:472.77pt;left:122.68pt;z-index:815;"} case, it is the recommended way of loading constants.
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%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 35
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%div{:style => "position:absolute;top:355.89pt;left:674.32pt;z-index:402;letter-spacing:.001em;"} e
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%div{:style => "position:absolute;top:355.89pt;left:691.84pt;z-index:404;letter-spacing:.001em;"} a
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:710.56pt;z-index:406;"} s
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:180.88pt;z-index:88;letter-spacing:.001em;"} Multiplication Instructions
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.439pt;z-index:144;"}
%span.fmt-107 *
The Basic ARM provides two multiplication instructions.
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:98.4399pt;z-index:153;letter-spacing:-.003em;"}
%span.fmt-107 *
Multiply
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:193;letter-spacing:-.004em;"} • MUL{&lt;cond&gt;}{S} Rd, Rm, Rs
%div{:style => "position:absolute;top:212.49pt;left:487pt;z-index:193;"} ; Rd = Rm * Rs
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:98.439pt;z-index:236;letter-spacing:-.001em;"}
%span.fmt-107 *
Multiply Accumulate
%div{:style => "position:absolute;top:241.17pt;left:331.6pt;z-index:236;letter-spacing:.001em;"} - does addition for free
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:286;letter-spacing:-.003em;"} • MLA{&lt;cond&gt;}{S} Rd, Rm, Rs,Rn
%div{:style => "position:absolute;top:269.85pt;left:487pt;z-index:286;"} ; Rd = (Rm * Rs) + Rn
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:298.53pt;left:98.4392pt;z-index:307;letter-spacing:-.001em;"}
%span.fmt-107 *
Restrictions on use:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.21pt;left:137.32pt;z-index:345;letter-spacing:-.004em;"} • Rd and Rm cannot be the same register
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:176.2pt;z-index:401;letter-spacing:-.001em;"} Can be avoid by swapping Rm and Rs around. This works b
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:377.37pt;left:195.64pt;z-index:438;letter-spacing:-.001em;"} multiplication is commutative.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:406.05pt;left:137.32pt;z-index:453;letter-spacing:-.007em;"} • Cannot use PC.
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:434.73pt;left:122.68pt;z-index:508;"} These will be picked up by the assembler if overlooked.
%span.fmt-108{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:463.41pt;left:98.4378pt;z-index:554;"}
%span.fmt-107 *
Operands can be considered signed or unsigned
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:492.21pt;left:137.32pt;z-index:589;letter-spacing:-.003em;"} • Up to user to interpret correctly.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
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%div{:style => "position:absolute;top:355.89pt;left:700.72pt;z-index:405;"} u
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%span.fmt-0{:style => "white-space:pre;"}
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.fmt-110{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-109{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:262.65pt;left:700.84pt;z-index:360;letter-spacing:.001em;"} i
%span.fmt-111{:style => "white-space:pre;"}
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%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:148.72pt;z-index:90;letter-spacing:.001em;"} Multiplication Implementation
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.439pt;z-index:149;"}
%span.fmt-109 *
The ARM makes use of Booths Algorithm to perform integer
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:165;letter-spacing:.001em;"} multiplication.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:205.17pt;left:98.4399pt;z-index:220;"}
%span.fmt-109 *
On non-M ARMs this operates on 2 bits of Rs at a time.
%span.fmt-109{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:233.97pt;left:138.4pt;z-index:291;letter-spacing:-.002em;"} • For each pair of bits this takes 1 cycle (plus 1 cycle to start with).
%span.fmt-109{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:262.65pt;left:138.4pt;z-index:359;letter-spacing:-.005em;"} • However when there are no more 1 s left in Rs, the multiplication w
%span.fmt-109{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:284.13pt;left:157.84pt;z-index:380;"} early-terminate.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:312.81pt;left:98.4391pt;z-index:423;"}
%span.fmt-109 *
Example: Multiply 18 and -1 : Rd = Rm * Rs
%span.fmt-37{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:360.69pt;left:97.7187pt;z-index:676;letter-spacing:-.001em;"}
%span.fmt-111 R
%span.fmt-111 m
%div{:style => "position:absolute;top:360.69pt;left:165.04pt;z-index:676;letter-spacing:.003em;"}
%span.fmt-111{:style => "position:relative;left:0pt;top:2pt;"} 1
%span.fmt-111{:style => "position:relative;left:0pt;top:2pt;"} 8
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
%span{:style => "position:relative;left:0pt;top:5pt;"}
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
%span{:style => "position:relative;left:0pt;top:5pt;"}
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
%span{:style => "position:relative;left:0pt;top:5pt;"}
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
%span{:style => "position:relative;left:0pt;top:5pt;"}
%span{:style => "position:relative;left:0pt;top:5pt;"} 0
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%div{:style => "position:absolute;top:552.8pt;left:102.64pt;z-index:10;"} M
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
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%div{:style => "position:absolute;top:70.3622pt;left:139.96pt;z-index:91;letter-spacing:.001em;"} Extended Multiply Instructions
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%span.fmt-112 *
M variants of ARM cores contain extended multiplication
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%div{:style => "position:absolute;top:180.93pt;left:148pt;z-index:191;"} hardware. This provides three enhancements:
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%span.fmt-112 •
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= succeed "8" do
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%div{:style => "position:absolute;top:238.41pt;left:201.52pt;z-index:286;letter-spacing:-.001em;"} Multiplication is carried out faster (maximum for standard
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%div{:style => "position:absolute;top:259.89pt;left:220.96pt;z-index:316;"} instructions is now 5 cycles).
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%div{:style => "position:absolute;top:288.57pt;left:162.64pt;z-index:373;letter-spacing:-.002em;"}
%span.fmt-112 •
Early termination method improved
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%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:310.05pt;left:182.08pt;z-index:424;letter-spacing:-.001em;"} multiplication when all remaining bit sets contain
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:338.73pt;left:201.52pt;z-index:460;letter-spacing:-.001em;"} all zeroes (as with non-M ARMs), or
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%div{:style => "position:absolute;top:367.41pt;left:201.52pt;z-index:471;letter-spacing:-.002em;"} all ones.
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%div{:style => "position:absolute;top:396.09pt;left:182.08pt;z-index:534;"} Thus the previous example would early terminate in 2 cycles in
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%div{:style => "position:absolute;top:417.57pt;left:182.08pt;z-index:545;letter-spacing:-.001em;"} both cases.
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%span.fmt-114 6
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= succeed "can" do
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%div{:style => "position:absolute;top:475.05pt;left:201.52pt;z-index:621;letter-spacing:-.002em;"} Higher accuracy.
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%div{:style => "position:absolute;top:503.73pt;left:201.52pt;z-index:661;letter-spacing:-.001em;"} Pair of registers used to store result.
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%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:58;"} Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:49.3622pt;left:255.4pt;z-index:78;letter-spacing:.001em;"} Multiply-Long and
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%div{:style => "position:absolute;top:91.242pt;left:179.8pt;z-index:102;letter-spacing:.001em;"} Multiply-Accumulate Long
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%span.fmt-115 *
Instructions are
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:167;letter-spacing:-.002em;"} • MULL which gives RdHi,RdLo:=Rm*Rs
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%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:213;letter-spacing:-.002em;"} • MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
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%div{:style => "position:absolute;top:241.17pt;left:98.439pt;z-index:280;"}
%span.fmt-115 *
However the full 64 bit of the result now matter (lower precision
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%div{:style => "position:absolute;top:262.65pt;left:122.68pt;z-index:332;letter-spacing:.001em;"} multiply instructions simply throws top 32bits away)
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:388;letter-spacing:-.002em;"} • Need to specify whether operands are signed or unsigned
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%span.fmt-115 *
Therefore syntax of new instructions are:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:348.69pt;left:137.32pt;z-index:463;letter-spacing:-.003em;"} • UMULL{&lt;cond&gt;}{S} RdLo,RdHi,Rm,Rs
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%div{:style => "position:absolute;top:377.37pt;left:137.32pt;z-index:496;letter-spacing:-.003em;"} • UMLAL{&lt;cond&gt;}{S} RdLo,RdHi,Rm,Rs
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%div{:style => "position:absolute;top:406.05pt;left:137.32pt;z-index:532;letter-spacing:-.003em;"} • SMULL{&lt;cond&gt;}{S} RdLo, RdHi, Rm, Rs
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%div{:style => "position:absolute;top:434.73pt;left:137.32pt;z-index:568;letter-spacing:-.003em;"} • SMLAL{&lt;cond&gt;}{S} RdLo, RdHi, Rm, Rs
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%span.fmt-115 *
Not generated by the compiler.
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%div{:style => "position:absolute;top:493.99pt;left:122.68pt;z-index:637;letter-spacing:-.001em;"} Warning : Unpredictable on non-M ARMs.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:285.45pt;left:610.84pt;z-index:290;"} #
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%div{:style => "position:absolute;top:70.3622pt;left:353.44pt;z-index:68;letter-spacing:.001em;"} Quiz #3
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%div{:style => "position:absolute;top:129.45pt;left:100.96pt;z-index:127;letter-spacing:.001em;"} 1. Specify instructions which will implement the following:
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%div{:style => "position:absolute;top:160.65pt;left:140.32pt;z-index:153;letter-spacing:.001em;"} a) r0 = 16
%div{:style => "position:absolute;top:160.65pt;left:493.48pt;z-index:153;letter-spacing:.001em;"} b) r1 = r0 * 4
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%div{:style => "position:absolute;top:191.85pt;left:140.32pt;z-index:205;"} c) r0 = r1 / 16 ( r1 signed 2's comp.)
%div{:style => "position:absolute;top:191.85pt;left:493.48pt;z-index:205;letter-spacing:.001em;"} d) r1 = r2 * 7
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%div{:style => "position:absolute;top:254.25pt;left:100.96pt;z-index:248;letter-spacing:.001em;"} 2. What will the following instructions do?
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%div{:style => "position:absolute;top:285.45pt;left:140.32pt;z-index:289;letter-spacing:.001em;"} a) ADDS r0, r1, r1, LSL #2
%div{:style => "position:absolute;top:285.45pt;left:493.48pt;z-index:289;letter-spacing:.001em;"} b) RSB r2, r1,
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%div{:style => "position:absolute;top:342.69pt;left:100.96pt;z-index:342;letter-spacing:.001em;"} 3. What does the following instruction sequence do?
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%div{:style => "position:absolute;top:371.37pt;left:140.32pt;z-index:364;letter-spacing:.001em;"} ADD r0, r1, r1, LSL #1
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%div{:style => "position:absolute;top:400.05pt;left:140.32pt;z-index:386;"} SUB r0, r0, r1, LSL #4
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%div{:style => "position:absolute;top:428.73pt;left:140.32pt;z-index:408;letter-spacing:.001em;"} ADD r0, r0, r1, LSL #7
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
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%div{:style => "position:absolute;top:70.3622pt;left:193.84pt;z-index:86;letter-spacing:.001em;"} Load / Store Instructions
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%span.fmt-120 *
The ARM is a Load / Store Architecture:
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%div{:style => "position:absolute;top:181.77pt;left:160.96pt;z-index:188;letter-spacing:-.002em;"} • Does not support memory to memory data processing operations.
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%div{:style => "position:absolute;top:210.45pt;left:160.96pt;z-index:244;letter-spacing:-.003em;"} • Must move data values into registers before using them.
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%span.fmt-120 *
This might sound inefficient, but in practice isnt:
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%div{:style => "position:absolute;top:267.81pt;left:160.96pt;z-index:342;letter-spacing:-.003em;"} • Load data values from memory into registers.
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%div{:style => "position:absolute;top:296.49pt;left:160.96pt;z-index:403;letter-spacing:-.002em;"} • Process data in registers using a number of data processing
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%div{:style => "position:absolute;top:318.09pt;left:180.4pt;z-index:459;"} instructions which are not slowed down by memory access.
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%div{:style => "position:absolute;top:346.77pt;left:160.96pt;z-index:503;letter-spacing:-.003em;"} • Store results from registers out to memory.
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%span.fmt-120 *
The ARM has three sets of instructions which interact with main
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%div{:style => "position:absolute;top:396.93pt;left:146.32pt;z-index:586;"} memory. These are:
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%div{:style => "position:absolute;top:425.61pt;left:160.96pt;z-index:629;letter-spacing:-.003em;"} • Single register data transfer (LDR / STR).
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%div{:style => "position:absolute;top:454.29pt;left:160.96pt;z-index:660;letter-spacing:-.004em;"} • Block data transfer (LDM/STM).
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%div{:style => "position:absolute;top:482.97pt;left:160.96pt;z-index:684;letter-spacing:-.005em;"} • Single Data Swap (SWP).
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%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:58;"} Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:241.17pt;left:730.36pt;z-index:255;"} d
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%div{:style => "position:absolute;top:70.3622pt;left:164.68pt;z-index:90;letter-spacing:.001em;"} Single register data transfer
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%span.fmt-122 *
The basic load and store instructions are:
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:161;letter-spacing:-.004em;"} • Load and Store Word or Byte
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%div{:style => "position:absolute;top:212.49pt;left:176.2pt;z-index:185;"} LDR / STR / LDRB / STRB
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%div{:style => "position:absolute;top:241.17pt;left:98.439pt;z-index:254;"}
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ARM Architecture Version 4 also adds support for halfwords and signe
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%div{:style => "position:absolute;top:262.65pt;left:122.68pt;z-index:261;letter-spacing:.001em;"} data.
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:285;letter-spacing:-.005em;"} • Load and Store Halfword
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%div{:style => "position:absolute;top:320.01pt;left:176.2pt;z-index:297;letter-spacing:-.001em;"} LDRH / STRH
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%div{:style => "position:absolute;top:348.69pt;left:137.32pt;z-index:369;letter-spacing:-.002em;"} • Load Signed Byte or Halfword - load value and sign extend it to 32 bits.
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%div{:style => "position:absolute;top:377.37pt;left:176.2pt;z-index:383;letter-spacing:-.001em;"} LDRSB / LDRSH
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%span.fmt-122 *
All of these instructions can be conditionally executed by inserting the
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%div{:style => "position:absolute;top:427.53pt;left:122.68pt;z-index:500;"} appropriate condition code after STR / LDR.
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%div{:style => "position:absolute;top:456.21pt;left:137.32pt;z-index:512;letter-spacing:-.008em;"} • e.g. LDREQB
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%span.fmt-122 *
Syntax:
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%div{:style => "position:absolute;top:513.69pt;left:137.32pt;z-index:560;letter-spacing:-.002em;"} • &lt;LDR|STR&gt;{&lt;cond&gt;}{&lt;size&gt;} Rd, &lt;address&gt;
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:49.3622pt;left:147.64pt;z-index:89;letter-spacing:.001em;"} Load and Store Word or Byte:
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%div{:style => "position:absolute;top:91.242pt;left:298.36pt;z-index:102;letter-spacing:.001em;"} Base Register
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The memory location to be accessed is held in a base register
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:222;letter-spacing:-.007em;"} • STR r0, [r1]
%div{:style => "position:absolute;top:183.69pt;left:331.6pt;z-index:222;"} ; Store contents of r0 to location pointed to
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%div{:style => "position:absolute;top:205.17pt;left:331.6pt;z-index:242;"} ; by contents of r1.
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:297;letter-spacing:-.007em;"} • LDR r2, [r1]
%div{:style => "position:absolute;top:233.97pt;left:331.6pt;z-index:297;"} ; Load r2 with contents of memory location
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:255.45pt;left:331.6pt;z-index:328;"} ; pointed to by contents of r1.
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%div{:style => "position:absolute;top:300.96pt;left:227.08pt;z-index:375;letter-spacing:-.002em;"} r0
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%span{:style => "position:relative;left:0pt;top:-2pt;"} e
%span{:style => "position:relative;left:0pt;top:-2pt;"} m
%span{:style => "position:relative;left:0pt;top:-2pt;"} o
%span{:style => "position:relative;left:0pt;top:-2pt;"} r
%span{:style => "position:relative;left:0pt;top:-2pt;"} y
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%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:122.44pt;z-index:379;letter-spacing:.001em;"} S
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:117.28pt;z-index:385;"} R
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:133.6pt;z-index:380;letter-spacing:.001em;"} o
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:129.4pt;z-index:386;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:138.64pt;z-index:387;letter-spacing:.001em;"} g
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:143.8pt;z-index:381;letter-spacing:.001em;"} u
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:148.96pt;z-index:388;letter-spacing:.001em;"} i
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:154.12pt;z-index:382;"} r
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:153.64pt;z-index:389;"} s
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:160.6pt;z-index:383;"} c
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:163pt;z-index:390;"} t
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:317.52pt;left:169.96pt;z-index:384;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:168.64pt;z-index:391;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:335.64pt;left:178pt;z-index:392;"} r
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:328.44pt;left:219.88pt;z-index:376;"} 0
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:328.44pt;left:229.24pt;z-index:377;"} x
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:328.44pt;left:238.6pt;z-index:378;"} 5
%img{:alt => "__rendered_path__329", :src => "./target/c03c41f04babeae71510fd976a2e9818.png", :style => "position:absolute;left:203.92pt;top:330.68pt;width:72pt;height:24pt;z-index:329;"}/
%img{:alt => "__rendered_path__372", :src => "./target/49a38623bafd9e3d8b36ded0dd3abd32.png", :style => "position:absolute;left:197.56pt;top:324.32pt;width:72pt;height:24pt;z-index:372;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:353.88pt;left:120.64pt;z-index:399;letter-spacing:.001em;"} for STR
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:436.2pt;left:86.44pt;z-index:421;letter-spacing:-.001em;"} Base
%div{:style => "position:absolute;top:436.2pt;left:182.68pt;z-index:421;letter-spacing:-.002em;"}
%span{:style => "position:relative;left:0pt;top:-17pt;"} r
%span{:style => "position:relative;left:0pt;top:-17pt;"} 1
%div{:style => "position:absolute;top:436.2pt;left:554.68pt;z-index:421;letter-spacing:-.002em;"}
%span{:style => "position:relative;left:0pt;top:-12pt;"} r
%span{:style => "position:relative;left:0pt;top:-12pt;"} 2
%div{:style => "position:absolute;top:436.2pt;left:605.68pt;z-index:421;"}
%span{:style => "position:relative;left:0pt;top:-2pt;"} D
%span{:style => "position:relative;left:0pt;top:-2pt;"} e
%span{:style => "position:relative;left:0pt;top:-2pt;"} s
%span{:style => "position:relative;left:0pt;top:-2pt;"} t
%span{:style => "position:relative;left:0pt;top:-2pt;"} i
%span{:style => "position:relative;left:0pt;top:-2pt;"} n
%span{:style => "position:relative;left:0pt;top:-2pt;"} a
%span{:style => "position:relative;left:0pt;top:-2pt;"} t
%span{:style => "position:relative;left:0pt;top:-2pt;"} i
%span{:style => "position:relative;left:0pt;top:-2pt;"} o
%span{:style => "position:relative;left:0pt;top:-2pt;"} n
%img{:alt => "__rendered_path__439", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:439;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:454.44pt;left:72.88pt;z-index:429;letter-spacing:.001em;"} Register
%div{:style => "position:absolute;top:454.44pt;left:166.12pt;z-index:429;letter-spacing:-.001em;"}
%span{:style => "position:relative;left:0pt;top:-7pt;"} 0
%span{:style => "position:relative;left:0pt;top:-7pt;"} x
%span{:style => "position:relative;left:0pt;top:-7pt;"} 2
%span{:style => "position:relative;left:0pt;top:-7pt;"} 0
%span{:style => "position:relative;left:0pt;top:-7pt;"} 0
%div{:style => "position:absolute;top:454.44pt;left:293.68pt;z-index:429;letter-spacing:-.001em;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} 0
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} x
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} 2
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} 0
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} 0
%div{:style => "position:absolute;top:454.44pt;left:379.12pt;z-index:429;letter-spacing:.001em;"}
%span{:style => "position:relative;left:0pt;top:-1pt;"} 0
%span{:style => "position:relative;left:0pt;top:-1pt;"} x
%span{:style => "position:relative;left:0pt;top:-1pt;"} 5
%div{:style => "position:absolute;top:454.44pt;left:547.48pt;z-index:429;letter-spacing:.001em;"}
%span{:style => "position:relative;left:0pt;top:-3pt;"} 0
%span{:style => "position:relative;left:0pt;top:-3pt;"} x
%span{:style => "position:relative;left:0pt;top:-3pt;"} 5
%div{:style => "position:absolute;top:454.44pt;left:617.8pt;z-index:429;letter-spacing:.001em;"}
%span{:style => "position:relative;left:0pt;top:-2pt;"} R
%span{:style => "position:relative;left:0pt;top:-2pt;"} e
%span{:style => "position:relative;left:0pt;top:-2pt;"} g
%span{:style => "position:relative;left:0pt;top:-2pt;"} i
%span{:style => "position:relative;left:0pt;top:-2pt;"} s
%span{:style => "position:relative;left:0pt;top:-2pt;"} t
%span{:style => "position:relative;left:0pt;top:-2pt;"} e
%span{:style => "position:relative;left:0pt;top:-2pt;"} r
%img{:alt => "__rendered_path__329", :src => "./target/c03c41f04babeae71510fd976a2e9818.png", :style => "position:absolute;left:159.52pt;top:449.36pt;width:72pt;height:24pt;z-index:329;"}/
%img{:alt => "__rendered_path__331", :src => "./target/cbbc926574abfd0d381749aadab337f6.png", :style => "position:absolute;left:153.16pt;top:443.12pt;width:72pt;height:24pt;z-index:331;"}/
%img{:alt => "__rendered_path__352", :src => "./target/dc84a4364ebd5c27b636a9b93f8e7301.png", :style => "position:absolute;left:276.64pt;top:455pt;width:14pt;height:9pt;z-index:352;"}/
%img{:alt => "__rendered_path__401", :src => "./target/cec2757599d1572094c9e5aa6b150ec6.png", :style => "position:absolute;left:334.84pt;top:441.44pt;width:15pt;height:18pt;z-index:401;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:471pt;left:620.56pt;z-index:436;"} for LDR
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "Image_457_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__402", :src => "./target/2e6d86ad4d4d2152b5d5e70c88ee0e45.png", :style => "position:absolute;left:530.92pt;top:454.04pt;width:73pt;height:24pt;z-index:402;"}/
%img{:alt => "__rendered_path__404", :src => "./target/905f4607b5756e6c39969deb2aaf5a6c.png", :style => "position:absolute;left:524.56pt;top:447.8pt;width:73pt;height:24pt;z-index:404;"}/
%img{:alt => "__rendered_path__438", :src => "./target/d00f30b999cf2af12d0fdf2e19ed13e8.png", :style => "position:absolute;left:495.16pt;top:456.44pt;width:18pt;height:12pt;z-index:438;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:58;"} The ARM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 43
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 44
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-127{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:139.12pt;z-index:16;"} r
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:154.29pt;left:120.52pt;z-index:120;"} *
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:225.93pt;left:120.52pt;z-index:273;"} *
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:311.97pt;left:120.52pt;z-index:399;"} *
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:369.45pt;left:120.52pt;z-index:524;"} *
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:15;"} The ARM Inst
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:147.64pt;z-index:89;letter-spacing:.001em;"} Load and Store Word or Byte:
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:143.08pt;z-index:119;letter-spacing:.001em;"} Offsets from the Base Register
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:154.29pt;left:144.76pt;z-index:193;"} As well as accessing the actual location contained in the base register,
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:175.77pt;left:144.76pt;z-index:264;"} these instructions can access a location offset from the base register
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:197.25pt;left:144.76pt;z-index:272;letter-spacing:.001em;"} pointer.
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:225.93pt;left:144.76pt;z-index:291;"} This offset can be
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:254.61pt;left:159.4pt;z-index:345;letter-spacing:-.002em;"} • An unsigned 12bit immediate value (ie 0 - 4095 bytes).
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:283.29pt;left:159.4pt;z-index:398;letter-spacing:-.003em;"} • A register, optionally shifted by an immediate value
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:311.97pt;left:144.76pt;z-index:461;"} This can be either added or subtracted from the base register:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:340.65pt;left:159.4pt;z-index:523;letter-spacing:-.009em;"}
• Prefix the offset value or register with
%span.fmt-128> +
(default) or
%span.fmt-128> -
.
%span.fmt-128{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:369.45pt;left:144.76pt;z-index:551;"} This offset can be applied:
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:398.13pt;left:159.4pt;z-index:603;letter-spacing:-.003em;"}
• before the transfer is made:
%span.fmt-63 P
%span.fmt-63 r
%span.fmt-63 e
%span.fmt-63 -
%span.fmt-63 i
%span.fmt-63 n
%span.fmt-63 d
%span.fmt-63 e
%span.fmt-63 x
%span.fmt-63 e
%span.fmt-63 d
%span.fmt-63
%span.fmt-63 a
%span.fmt-63 d
%span.fmt-63 d
%span.fmt-63 r
%span.fmt-63 e
%span.fmt-63 s
%span.fmt-63 s
%span.fmt-63 i
%span.fmt-63 n
%span.fmt-63 g
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:426.81pt;left:194.56pt;z-index:669;letter-spacing:-.001em;"}
optionally
%span.fmt-129 a
%span.fmt-129 u
%span.fmt-129 t
%span.fmt-129 o
%span.fmt-129 -
%span.fmt-129 i
%span.fmt-129 n
%span.fmt-129 c
%span.fmt-129 r
%span.fmt-129 e
%span.fmt-129 m
%span.fmt-129 e
%span.fmt-129 n
%span.fmt-129 t
%span.fmt-129 i
%span.fmt-129 n
%span.fmt-129 g
%span t
%span h
%span e
%span
%span b
%span a
%span s
%span e
%span
%span r
%span e
%span g
%span i
%span s
%span t
%span e
%span r
%span ,
%span
%span b
%span y
%span
%span p
%span o
%span s
%span t
%span f
%span i
%span x
%span i
%span n
%span g
%span
%span t
%span h
%span e
%span
%img{:alt => "__rendered_path__615", :src => "./target/e6ea1b32db4523787cef7c162737e41d.png", :style => "position:absolute;left:214.12pt;top:445.88pt;width:81pt;height:3pt;z-index:615;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:448.29pt;left:214.12pt;z-index:693;letter-spacing:-.01em;"}
instruction with an
%span.fmt-128> !
.
%img{:alt => "__rendered_path__796", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:796;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:476.97pt;left:159.4pt;z-index:745;letter-spacing:-.002em;"}
• after the transfer is made:
%span.fmt-63 P
%span.fmt-63 o
%span.fmt-63 s
%span.fmt-63 t
%span.fmt-63 -
%span.fmt-63 i
%span.fmt-63 n
%span.fmt-63 d
%span.fmt-63 e
%span.fmt-63 x
%span.fmt-63 e
%span.fmt-63 d
%span.fmt-63
%span.fmt-63 a
%span.fmt-63 d
%span.fmt-63 d
%span.fmt-63 r
%span.fmt-63 e
%span.fmt-63 s
%span.fmt-63 s
%span.fmt-63 i
%span.fmt-63 n
%span.fmt-63 g
%img{:alt => "Image_467_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:505.65pt;left:194.56pt;z-index:795;letter-spacing:-.001em;"}
causing the base register to be
%span.fmt-129 a
%span.fmt-129 u
%span.fmt-129 t
%span.fmt-129 o
%span.fmt-129 -
%span.fmt-129 i
%span.fmt-129 n
%span.fmt-129 c
%span.fmt-129 r
%span.fmt-129 e
%span.fmt-129 m
%span.fmt-129 e
%span.fmt-129 n
%span.fmt-129 t
%span.fmt-129 e
= succeed "." do
%span.fmt-129 d
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:144.04pt;z-index:58;letter-spacing:-.001em;"} uction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 44
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 45
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-131{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:662.8pt;z-index:88;"} e
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:147.64pt;z-index:87;letter-spacing:.001em;"} Load and Store Word or Byt
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:199.24pt;z-index:111;letter-spacing:.001em;"} Pre-indexed Addressing
%span.fmt-130{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.4389pt;z-index:390;letter-spacing:-.001em;"}
*
%span.fmt-131 E
%span.fmt-131 x
%span.fmt-131 a
%span.fmt-131 m
%span.fmt-131 p
%span.fmt-131 l
%span.fmt-131 e
%span.fmt-131 :
= succeed "STR" do
%span.fmt-131
%div{:style => "position:absolute;top:155.01pt;left:464.32pt;z-index:390;"}
%span.fmt-73 M
%span.fmt-73 e
%span.fmt-73 m
%span.fmt-73 o
%span.fmt-73 r
%span.fmt-73 y
%div{:style => "position:absolute;top:155.01pt;left:638.2pt;z-index:390;letter-spacing:-.001em;"}
%span.fmt-73{:style => "position:relative;left:0pt;top:-12pt;"} r
%span.fmt-73{:style => "position:relative;left:0pt;top:-12pt;"} 0
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:172.8pt;left:631.12pt;z-index:393;letter-spacing:.001em;"} 0x5
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:211.32pt;left:270.76pt;z-index:422;letter-spacing:.002em;"} Offset
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:238.92pt;left:287.8pt;z-index:429;letter-spacing:.001em;"} 12
%div{:style => "position:absolute;top:238.92pt;left:400.36pt;z-index:429;letter-spacing:-.001em;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-1pt;"} 0
%span.fmt-126{:style => "position:relative;left:0pt;top:-1pt;"} x
%span.fmt-126{:style => "position:relative;left:0pt;top:-1pt;"} 2
%span.fmt-126{:style => "position:relative;left:0pt;top:-1pt;"} 0
%span.fmt-126{:style => "position:relative;left:0pt;top:-1pt;"} c
%div{:style => "position:absolute;top:238.92pt;left:481.36pt;z-index:429;letter-spacing:.001em;"}
%span 0
%span x
%span 5
%img{:alt => "__rendered_path__416", :src => "./target/d00b598c88984941a5f9390a07affc65.png", :style => "position:absolute;left:537.28pt;top:227.88pt;width:17pt;height:17pt;z-index:416;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:275.04pt;left:188.92pt;z-index:346;letter-spacing:-.002em;"} r1
%img{:alt => "__rendered_path__342", :src => "./target/c03c41f04babeae71510fd976a2e9818.png", :style => "position:absolute;left:265.6pt;top:241.04pt;width:72pt;height:24pt;z-index:342;"}/
%img{:alt => "__rendered_path__344", :src => "./target/cbbc926574abfd0d381749aadab337f6.png", :style => "position:absolute;left:259.36pt;top:234.8pt;width:72pt;height:24pt;z-index:344;"}/
%img{:alt => "__rendered_path__433", :src => "./target/ce3a717688e12fdf459b94df25b295ea.png", :style => "position:absolute;left:384.28pt;top:244.4pt;width:14pt;height:9pt;z-index:433;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:79.12pt;z-index:356;"} R
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.6pt;left:92.6799pt;z-index:352;"} B
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:91.24pt;z-index:357;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.6pt;left:104.8pt;z-index:353;"} a
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:100.48pt;z-index:358;letter-spacing:.001em;"} g
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:110.8pt;z-index:359;letter-spacing:.001em;"} i
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.6pt;left:114.16pt;z-index:354;"} s
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:115.48pt;z-index:360;"} s
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.6pt;left:123.4pt;z-index:355;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:124.84pt;z-index:361;"} t
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:130.48pt;z-index:362;"} e
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.72pt;left:139.84pt;z-index:363;"} r
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:302.52pt;left:172.48pt;z-index:347;"} 0
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:302.52pt;left:181.84pt;z-index:348;"} x
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:302.52pt;left:191.2pt;z-index:349;"} 2
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:302.52pt;left:200.44pt;z-index:350;"} 0
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:302.52pt;left:209.8pt;z-index:351;"} 0
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.51pt;left:400.6pt;z-index:381;"} 0
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.51pt;left:408.76pt;z-index:382;"} x
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.51pt;left:415.96pt;z-index:383;"} 2
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.51pt;left:424.12pt;z-index:384;"} 0
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:309.51pt;left:432.28pt;z-index:385;"} 0
%img{:alt => "__rendered_path__342", :src => "./target/c03c41f04babeae71510fd976a2e9818.png", :style => "position:absolute;left:165.76pt;top:304.76pt;width:72pt;height:24pt;z-index:342;"}/
%img{:alt => "__rendered_path__344", :src => "./target/cbbc926574abfd0d381749aadab337f6.png", :style => "position:absolute;left:159.52pt;top:298.4pt;width:72pt;height:24pt;z-index:344;"}/
%img{:alt => "__rendered_path__365", :src => "./target/9c0fac81e27e20013588546ae64a9fd6.png", :style => "position:absolute;left:379.6pt;top:311.12pt;width:14pt;height:9pt;z-index:365;"}/
%img{:alt => "__rendered_path__431", :src => "./target/00ddb66eaafb5cd71cad19414d99c1ab.png", :style => "position:absolute;left:292.36pt;top:268.44pt;width:9pt;height:14pt;z-index:431;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:413.25pt;left:98.439pt;z-index:195;"}
%span.fmt-130 *
To store to location 0x1f4 instead use:
%span.fmt-130 S
%span.fmt-130 T
%span.fmt-130 R
%span.fmt-130
%span.fmt-130 r
%span.fmt-130 0
%span.fmt-130 ,
%span.fmt-130
%span.fmt-130 [
%span.fmt-130 r
%span.fmt-130 1
%span.fmt-130 ,
%span.fmt-130 #
%span.fmt-130 -
%span.fmt-130 1
%span.fmt-130 2
%span.fmt-130 ]
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:441.93pt;left:98.4402pt;z-index:259;"}
%span.fmt-130 *
To auto-increment base pointer to 0x20c use:
%span.fmt-130 S
%span.fmt-130 T
%span.fmt-130 R
%span.fmt-130
%span.fmt-130 r
%span.fmt-130 0
%span.fmt-130 ,
%span.fmt-130
%span.fmt-130 [
%span.fmt-130 r
%span.fmt-130 1
%span.fmt-130 ,
%span.fmt-130
%span.fmt-130 #
%span.fmt-130 1
%span.fmt-130 2
%span.fmt-130 ]
%span.fmt-130 !
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:470.73pt;left:98.4393pt;z-index:316;"}
%span.fmt-130 *
If r2 contains 3, access 0x20c by multiplying this by 4:
%span.fmt-130{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:499.41pt;left:137.32pt;z-index:341;letter-spacing:-.004em;"} • STR r0, [r1, r2, LSL #2]
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%img{:alt => "__rendered_path__343", :src => "./target/0b1ab203ddc2d22f13517a3c3821d8c7.png", :style => "position:absolute;left:164.74pt;top:303.78pt;width:73.8pt;height:26pt;z-index:343;"}/
%img{:alt => "__rendered_path__343", :src => "./target/0b1ab203ddc2d22f13517a3c3821d8c7.png", :style => "position:absolute;left:158.5pt;top:297.42pt;width:73.8pt;height:26pt;z-index:343;"}/
%img{:alt => "__rendered_path__364", :src => "./target/99965ba542a6d43b2a61cb36ef9e7105.png", :style => "position:absolute;left:248.8pt;top:315pt;width:135.3pt;height:1.1pt;z-index:364;"}/
%img{:alt => "__rendered_path__372", :src => "./target/7ccf74abdb652e7e38d227b3bb6e7cd9.png", :style => "position:absolute;left:457.9pt;top:178.76pt;width:74pt;height:56.7pt;z-index:372;"}/
%img{:alt => "__rendered_path__373", :src => "./target/6dd2d0f915f577851c90921933741208.png", :style => "position:absolute;left:493.9pt;top:183.5pt;width:2.1pt;height:44.1pt;z-index:373;"}/
%img{:alt => "__rendered_path__386", :src => "./target/1c398d6d80af9fb26781eeb49a6da00c.png", :style => "position:absolute;left:614.02pt;top:174.06pt;width:73.9pt;height:26pt;z-index:386;"}/
%img{:alt => "__rendered_path__388", :src => "./target/ede8d93913f22b0dbc0c64b79efc8ac3.png", :style => "position:absolute;left:607.66pt;top:167.9pt;width:74pt;height:25.8pt;z-index:388;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:684.4pt;z-index:89;"} :
%img{:alt => "__rendered_path__374", :src => "./target/4db345ae3000b1c829da26bc7a315efe.png", :style => "position:absolute;left:457.9pt;top:258.86pt;width:74pt;height:23.4pt;z-index:374;"}/
%img{:alt => "__rendered_path__374", :src => "./target/4db345ae3000b1c829da26bc7a315efe.png", :style => "position:absolute;left:457.9pt;top:235.46pt;width:74pt;height:23.4pt;z-index:374;"}/
%img{:alt => "__rendered_path__415", :src => "./target/01d9f8215726f69ac90ec8ae868419d3.png", :style => "position:absolute;left:544.97pt;top:185.85pt;width:52.8pt;height:51.6pt;z-index:415;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:154.8pt;left:700.12pt;z-index:399;"} Source
%img{:alt => "__rendered_path__375", :src => "./target/910ffc932a9edd31c5551bb4cc851a20.png", :style => "position:absolute;left:457.9pt;top:305.64pt;width:74pt;height:23.3pt;z-index:375;"}/
%img{:alt => "__rendered_path__376", :src => "./target/fa308fa4d6a57eee8712d480012be93d.png", :style => "position:absolute;left:457.9pt;top:282.06pt;width:74pt;height:23.6pt;z-index:376;"}/
%img{:alt => "__rendered_path__343", :src => "./target/0b1ab203ddc2d22f13517a3c3821d8c7.png", :style => "position:absolute;left:264.58pt;top:240.06pt;width:73.8pt;height:26pt;z-index:343;"}/
%img{:alt => "__rendered_path__343", :src => "./target/0b1ab203ddc2d22f13517a3c3821d8c7.png", :style => "position:absolute;left:258.34pt;top:233.82pt;width:73.8pt;height:26pt;z-index:343;"}/
%img{:alt => "__rendered_path__432", :src => "./target/5d2e18d7686f4e6b1627d33a0259105d.png", :style => "position:absolute;left:341.56pt;top:248.28pt;width:47.2pt;height:1.1pt;z-index:432;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:172.92pt;left:694.96pt;z-index:407;letter-spacing:.001em;"} Register
%img{:alt => "__rendered_path__377", :src => "./target/c05d201af2833917f15f6f5ace5880bc.png", :style => "position:absolute;left:457.9pt;top:328.9pt;width:74pt;height:59.8pt;z-index:377;"}/
%img{:alt => "__rendered_path__373", :src => "./target/6dd2d0f915f577851c90921933741208.png", :style => "position:absolute;left:493.9pt;top:339.86pt;width:2.1pt;height:44.1pt;z-index:373;"}/
%img{:alt => "__rendered_path__430", :src => "./target/ee2622ef82be3d71485d3c13d6b085b2.png", :style => "position:absolute;left:296.26pt;top:277.8pt;width:1.1pt;height:38.6pt;z-index:430;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:191.16pt;left:698.32pt;z-index:414;letter-spacing:.001em;"} for STR
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "Image_478_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__342", :src => "./target/c03c41f04babeae71510fd976a2e9818.png", :style => "position:absolute;left:615.04pt;top:175.04pt;width:72pt;height:24pt;z-index:342;"}/
%img{:alt => "__rendered_path__387", :src => "./target/49a38623bafd9e3d8b36ded0dd3abd32.png", :style => "position:absolute;left:608.68pt;top:168.68pt;width:72pt;height:24pt;z-index:387;"}/
%img{:alt => "__rendered_path__434", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:434;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 45
%div{:style => "width:100%"}
%hr/
%table{:style => "border:0;width:100%;"}
%tbody
%tr
%td{:align => "right", :bgcolor => "eeeeee"}
%font{:face => "arial,sans-serif"}
%b Page 46
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-133{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%img{:alt => "__rendered_path__335", :src => "./target/389cbd4255406a19d33e9b72bc5d4105.png", :style => "position:absolute;left:169.42pt;top:345.12pt;width:74.6pt;height:26.9pt;z-index:335;"}/
%img{:alt => "__rendered_path__337", :src => "./target/fbcf18440beafb79728d1aee5130966e.png", :style => "position:absolute;left:163.18pt;top:338.78pt;width:74.6pt;height:27pt;z-index:337;"}/
%img{:alt => "__rendered_path__365", :src => "./target/a7c7f3d0388c780fc3118f4e659e0256.png", :style => "position:absolute;left:327.4pt;top:311.88pt;width:59.7pt;height:1.1pt;z-index:365;"}/
%img{:alt => "__rendered_path__373", :src => "./target/c97a2af89325a355139c9757789a78cf.png", :style => "position:absolute;left:459.46pt;top:167.24pt;width:74.7pt;height:59.1pt;z-index:373;"}/
%img{:alt => "__rendered_path__374", :src => "./target/775a345d6b75f7a9d3b9f05b0ebc7aba.png", :style => "position:absolute;left:495.82pt;top:172.22pt;width:2.1pt;height:45.9pt;z-index:374;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:147.64pt;z-index:89;letter-spacing:.001em;"} Load and Store Word or Byte:
%img{:alt => "__rendered_path__375", :src => "./target/0e64c353fd27a70377025fd99809ed65.png", :style => "position:absolute;left:459.46pt;top:250.78pt;width:74.7pt;height:24.4pt;z-index:375;"}/
%img{:alt => "__rendered_path__376", :src => "./target/7914e82d6887ffc039cf3218e7476540.png", :style => "position:absolute;left:459.46pt;top:226.34pt;width:74.7pt;height:24.6pt;z-index:376;"}/
%img{:alt => "__rendered_path__389", :src => "./target/27a7d6c6443da3500ed9ac795f75b889.png", :style => "position:absolute;left:602.98pt;top:222.48pt;width:74.7pt;height:26.9pt;z-index:389;"}/
%img{:alt => "__rendered_path__465", :src => "./target/592e267a8dbaafa51edcea4cb21acde8.png", :style => "position:absolute;left:253.48pt;top:240.36pt;width:30.4pt;height:1.1pt;z-index:465;"}/
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:188.44pt;z-index:112;letter-spacing:.001em;"} Post-indexed Addressing
%img{:alt => "__rendered_path__375", :src => "./target/0e64c353fd27a70377025fd99809ed65.png", :style => "position:absolute;left:459.46pt;top:299.62pt;width:74.7pt;height:24.4pt;z-index:375;"}/
%img{:alt => "__rendered_path__376", :src => "./target/7914e82d6887ffc039cf3218e7476540.png", :style => "position:absolute;left:459.46pt;top:275.06pt;width:74.7pt;height:24.6pt;z-index:376;"}/
%img{:alt => "__rendered_path__387", :src => "./target/798f15de211882bcea89fedc4a8b2643.png", :style => "position:absolute;left:609.22pt;top:228.74pt;width:74.7pt;height:27pt;z-index:387;"}/
%img{:alt => "__rendered_path__437", :src => "./target/444bb3fde59a138ad178846dddee1d56.png", :style => "position:absolute;left:163.9pt;top:224.7pt;width:74.7pt;height:27.2pt;z-index:437;"}/
%span.fmt-132{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:153.21pt;left:98.4399pt;z-index:372;letter-spacing:-.001em;"}
*
%span.fmt-133 E
%span.fmt-133 x
%span.fmt-133 a
%span.fmt-133 m
%span.fmt-133 p
%span.fmt-133 l
%span.fmt-133 e
%span.fmt-133 :
= succeed "STR" do
%span.fmt-133
%div{:style => "position:absolute;top:153.21pt;left:466.24pt;z-index:372;"}
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} M
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} e
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} m
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} o
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} r
%span.fmt-73{:style => "position:relative;left:0pt;top:-9pt;"} y
%img{:alt => "__rendered_path__377", :src => "./target/71e2b14b80327301baf3fe9e3a32cab3.png", :style => "position:absolute;left:459.46pt;top:324.02pt;width:74.7pt;height:62.4pt;z-index:377;"}/
%img{:alt => "__rendered_path__374", :src => "./target/775a345d6b75f7a9d3b9f05b0ebc7aba.png", :style => "position:absolute;left:495.82pt;top:335.42pt;width:2.1pt;height:45.9pt;z-index:374;"}/
%img{:alt => "__rendered_path__416", :src => "./target/f5dd40c1eef0b0fca0f842f03bfadb5a.png", :style => "position:absolute;left:548.8pt;top:253.36pt;width:53.5pt;height:53.8pt;z-index:416;"}/
%img{:alt => "__rendered_path__387", :src => "./target/798f15de211882bcea89fedc4a8b2643.png", :style => "position:absolute;left:294.46pt;top:235.1pt;width:74.7pt;height:27pt;z-index:387;"}/
%img{:alt => "__rendered_path__419", :src => "./target/15a740e7b1ea4fe7bd4c52522a47fef9.png", :style => "position:absolute;left:288.1pt;top:228.66pt;width:74.7pt;height:27.2pt;z-index:419;"}/
%span.fmt-73{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:209.4pt;left:94.84pt;z-index:451;letter-spacing:-.001em;"}
%span.fmt-134 U
%span.fmt-134 p
%span.fmt-134 d
%span.fmt-134 a
%span.fmt-134 t
%span.fmt-134 e
%span.fmt-134 d
%div{:style => "position:absolute;top:209.4pt;left:195.28pt;z-index:451;letter-spacing:.001em;"}
%span.fmt-134{:style => "position:relative;left:0pt;top:-7pt;"} r
%span.fmt-134{:style => "position:relative;left:0pt;top:-7pt;"} 1
%div{:style => "position:absolute;top:209.4pt;left:301pt;z-index:451;letter-spacing:.002em;"}
%span{:style => "position:relative;left:0pt;top:-4pt;"} O
%span{:style => "position:relative;left:0pt;top:-4pt;"} f
%span{:style => "position:relative;left:0pt;top:-4pt;"} f
%span{:style => "position:relative;left:0pt;top:-4pt;"} s
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%div{:style => "position:absolute;top:344.16pt;left:97.0001pt;z-index:356;letter-spacing:-.001em;"} Base
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%span 0
%span x
%span 2
%span 0
%span 0
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%div{:style => "position:absolute;top:362.4pt;left:83.4402pt;z-index:364;letter-spacing:.001em;"} Register
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%span.fmt-132 *
To auto-increment the base register to location 0x1f4 instead use:
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%div{:style => "position:absolute;top:411.57pt;left:137.32pt;z-index:225;letter-spacing:-.005em;"} • STR r0, [r1], #-12
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%div{:style => "position:absolute;top:437.85pt;left:98.4414pt;z-index:298;"}
%span.fmt-132 *
If r2 contains 3, auto-incremenet base register to 0x20c by multiplying
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%div{:style => "position:absolute;top:457.05pt;left:122.68pt;z-index:308;letter-spacing:.001em;"} this by 4:
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%div{:style => "position:absolute;top:483.33pt;left:137.32pt;z-index:333;letter-spacing:-.004em;"} • STR r0, [r1], r2, LSL #2
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%img{:alt => "Image_488_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
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%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:58;"} ARM Instruction Set - ARM University Program - V1.0
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 46
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%b Page 47
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%div{:style => "position:absolute;top:291.33pt;left:688.84pt;z-index:302;"} m
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%div{:style => "position:absolute;top:291.33pt;left:715.36pt;z-index:304;"} d
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
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%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:270.4pt;z-index:76;letter-spacing:.001em;"} Load and Stores
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%div{:style => "position:absolute;top:91.242pt;left:192.76pt;z-index:100;letter-spacing:.001em;"} with User Mode Privilege
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%span.fmt-135 *
When using post-indexed addressing, there is a further form of
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%div{:style => "position:absolute;top:205.17pt;left:122.68pt;z-index:185;"} Load/Store Word/Byte:
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• &lt;LDR|STR&gt;{&lt;cond&gt;}{B}
%span.fmt-136 T
Rd, &lt;post_indexed_address&gt;
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%span.fmt-135 *
When used in a privileged mode, this does the load/store with user
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%div{:style => "position:absolute;top:312.81pt;left:122.68pt;z-index:316;letter-spacing:-.001em;"} privilege.
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%div{:style => "position:absolute;top:341.49pt;left:137.32pt;z-index:381;letter-spacing:-.002em;"} • Normally used by an exception handler that is emulating a memory
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%div{:style => "position:absolute;top:362.97pt;left:156.76pt;z-index:441;letter-spacing:-.001em;"} access instruction that would normally execute in user mode.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%b Page 48
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%div{:style => "position:absolute;top:155.01pt;left:98.4398pt;z-index:94;"} *
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%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:255.28pt;z-index:77;letter-spacing:.001em;"} Example Usage of
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:248.8pt;z-index:93;letter-spacing:.001em;"} Addressing Modes
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:122.68pt;z-index:164;"} Imagine an array, the first element of which is pointed to by the cont
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:175;letter-spacing:.001em;"} of r0.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:205.17pt;left:122.68pt;z-index:662;"} If we want to access a particular element,
%div{:style => "position:absolute;top:205.17pt;left:590.08pt;z-index:662;letter-spacing:.001em;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} e
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} l
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} e
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} m
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} e
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} n
%span.fmt-126{:style => "position:relative;left:0pt;top:-3pt;"} t
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:226.77pt;left:122.68pt;z-index:257;"} then we can use pre-indexed addressing:
%span.fmt-137{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:255.45pt;left:137.32pt;z-index:280;letter-spacing:-.005em;"} • r1 is element we want.
%span.fmt-137{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:284.13pt;left:137.32pt;z-index:655;letter-spacing:-.004em;"} • LDR r2, [r0, r1, LSL #2]
.fmt-126{:style => "position:absolute;top:287.43pt;left:611.44pt;z-index:655;"} 3
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:311.07pt;left:487.72pt;z-index:693;letter-spacing:.001em;"} Pointer to
%div{:style => "position:absolute;top:311.07pt;left:612.16pt;z-index:693;"} 2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:334.29pt;left:122.68pt;z-index:707;letter-spacing:.001em;"} If we want to step through every
%div{:style => "position:absolute;top:334.29pt;left:478.12pt;z-index:707;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} s
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} t
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} a
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} r
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} t
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} o
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} f
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"}
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} a
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} r
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} r
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} a
%span.fmt-126{:style => "position:relative;left:0pt;top:-12pt;"} y
.fmt-126{:style => "position:absolute;top:334.59pt;left:611.44pt;z-index:707;"} 1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.77pt;left:122.68pt;z-index:682;"} element of the array, for instance
%div{:style => "position:absolute;top:355.77pt;left:458.68pt;z-index:682;letter-spacing:-.001em;"}
%span.fmt-73{:style => "position:relative;left:0pt;top:-1pt;"} r
%span.fmt-73{:style => "position:relative;left:0pt;top:-1pt;"} 0
.fmt-126{:style => "position:absolute;top:358.95pt;left:611.44pt;z-index:682;"} 0
%img{:alt => "__rendered_path__708", :src => "./target/99d7eac9ac79adaf291c12641f2d65da.png", :style => "position:absolute;left:488.08pt;top:354.2pt;width:72pt;height:24pt;z-index:708;"}/
%img{:alt => "__rendered_path__710", :src => "./target/ebcc90a22becb1b26011f94356a71c9c.png", :style => "position:absolute;left:481.72pt;top:347.96pt;width:72pt;height:24pt;z-index:710;"}/
%img{:alt => "__rendered_path__713", :src => "./target/978e5360660832ba85ffc508b807595c.png", :style => "position:absolute;left:591.88pt;top:359.84pt;width:18pt;height:12pt;z-index:713;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:377.25pt;left:122.68pt;z-index:405;letter-spacing:.001em;"} to produce sum of elements in the
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:398.73pt;left:122.68pt;z-index:466;"} array, then we can use post-indexed addressing within a loop:
%span.fmt-137{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:427.41pt;left:137.32pt;z-index:524;letter-spacing:-.002em;"} • r1 is address of current element (initially equal to r0).
%span.fmt-137{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:456.09pt;left:137.32pt;z-index:541;letter-spacing:-.006em;"} • LDR r2, [r1], #4
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:484.77pt;left:122.68pt;z-index:602;"} Use a further register to store the address of final element,
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:506.25pt;left:122.68pt;z-index:647;"} so that the loop can be correctly terminated.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:56;letter-spacing:-.001em;"} nstruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:713.92pt;z-index:169;letter-spacing:.001em;"} nts
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:194.67pt;left:713.2pt;z-index:670;letter-spacing:.001em;"} Mem
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:210.51pt;left:720.04pt;z-index:678;letter-spacing:.001em;"} Offs
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:287.43pt;left:730pt;z-index:667;letter-spacing:.001em;"} 12
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:311.07pt;left:734.08pt;z-index:665;"} 8
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:334.59pt;left:733.24pt;z-index:664;"} 4
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:358.23pt;left:734.08pt;z-index:663;"} 0
%img{:alt => "__rendered_path__648", :src => "./target/7ccf74abdb652e7e38d227b3bb6e7cd9.png", :style => "position:absolute;left:640.3pt;top:227.48pt;width:74pt;height:56.7pt;z-index:648;"}/
%img{:alt => "__rendered_path__649", :src => "./target/5250a89e2131bb39fa750921ef9aaf32.png", :style => "position:absolute;left:676.18pt;top:232.22pt;width:2.1pt;height:42.9pt;z-index:649;"}/
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:194.67pt;left:753.88pt;z-index:674;letter-spacing:-.004em;"} ry
%img{:alt => "__rendered_path__650", :src => "./target/4db345ae3000b1c829da26bc7a315efe.png", :style => "position:absolute;left:640.3pt;top:307.58pt;width:74pt;height:23.4pt;z-index:650;"}/
%img{:alt => "__rendered_path__650", :src => "./target/4db345ae3000b1c829da26bc7a315efe.png", :style => "position:absolute;left:640.3pt;top:284.18pt;width:74pt;height:23.4pt;z-index:650;"}/
%img{:alt => "__rendered_path__649", :src => "./target/5250a89e2131bb39fa750921ef9aaf32.png", :style => "position:absolute;left:614.86pt;top:233.78pt;width:2.1pt;height:42.9pt;z-index:649;"}/
%img{:alt => "__rendered_path__649", :src => "./target/5250a89e2131bb39fa750921ef9aaf32.png", :style => "position:absolute;left:739.06pt;top:233.06pt;width:2.1pt;height:42.9pt;z-index:649;"}/
%span.fmt-126{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:210.51pt;left:755.08pt;z-index:680;letter-spacing:.001em;"} t
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "Image_510_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%img{:alt => "__rendered_path__650", :src => "./target/4db345ae3000b1c829da26bc7a315efe.png", :style => "position:absolute;left:640.3pt;top:354.38pt;width:74pt;height:23.4pt;z-index:650;"}/
%img{:alt => "__rendered_path__651", :src => "./target/fa308fa4d6a57eee8712d480012be93d.png", :style => "position:absolute;left:640.3pt;top:330.78pt;width:74pt;height:23.6pt;z-index:651;"}/
%img{:alt => "__rendered_path__709", :src => "./target/081878f46f56275b6b2ed082ec770e7f.png", :style => "position:absolute;left:487.06pt;top:353.42pt;width:73.9pt;height:25.8pt;z-index:709;"}/
%img{:alt => "__rendered_path__711", :src => "./target/20e2035d6f3841c5ed4f1d7597f15d50.png", :style => "position:absolute;left:480.7pt;top:346.98pt;width:74pt;height:26pt;z-index:711;"}/
%img{:alt => "__rendered_path__712", :src => "./target/b14960889adad26facb62bbd7fb336e6.png", :style => "position:absolute;left:563.32pt;top:364.88pt;width:34.5pt;height:2.1pt;z-index:712;"}/
%img{:alt => "__rendered_path__714", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:714;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 48
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%b Page 49
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-140{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:715.12pt;z-index:245;"} h
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:49.3622pt;left:196pt;z-index:86;letter-spacing:.001em;"} Offsets for Halfword and
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:91.242pt;left:137.8pt;z-index:115;letter-spacing:.001em;"} Signed Halfword / Byte Access
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.439pt;z-index:177;"}
%span.fmt-139 *
The Load and Store Halfword and Load Signed Byte or Halfword
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:244;"} instructions can make use of pre- and post-indexed addressing in muc
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:197.97pt;left:122.68pt;z-index:300;"} the same way as the basic load and store instructions.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:226.77pt;left:98.4371pt;z-index:356;"}
%span.fmt-139 *
However the actual offset formats are more constrained:
%span.fmt-139{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:255.45pt;left:137.32pt;z-index:430;letter-spacing:-.002em;"} • The immediate value is limited to 8 bits (rather than 12 bits) giving an
%span.fmt-139{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:276.93pt;left:156.76pt;z-index:452;"} offset of 0-255 bytes.
%span.fmt-139{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:305.61pt;left:137.32pt;z-index:505;letter-spacing:-.002em;"} • The register form cannot have a shift applied to it.
%img{:alt => "Image_520_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
%img{:alt => "__rendered_path__2", :src => "./target/d00413d101e052af80bcbf4a2db40b96.png", :style => "position:absolute;left:56.56pt;top:536.12pt;width:719pt;height:.9pt;z-index:2;"}/
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:726.16pt;z-index:246;"}
%img{:alt => "__rendered_path__3", :src => "./target/c6053f756b075808893b5298e38e1f84.png", :style => "position:absolute;left:623.08pt;top:484.04pt;width:108pt;height:96pt;z-index:3;"}/
%img{:alt => "__rendered_path__59", :src => "./target/58efb4d00cfdb6014dbb515b1afcaef7.png", :style => "position:absolute;left:723.88pt;top:559.76pt;width:6pt;height:6pt;z-index:59;"}/
%img{:alt => "__rendered_path__60", :src => "./target/ce6513985399c0e12fc064993de3a583.png", :style => "position:absolute;left:723.82pt;top:560.22pt;width:5.6pt;height:5.6pt;z-index:60;"}/
%img{:alt => "__rendered_path__506", :src => "./target/0901647d626b9293db6430463286fe9d.png", :style => "position:absolute;left:43.12pt;top:14pt;width:755.8pt;height:567pt;z-index:506;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 49
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%b Page 50
%div{:style => "position:relative;width:842pt;height:595pt;"}
.fmt-142{:style => "position:absolute;left:0pt;top:0pt;width:100%;height:100%;clip:rect(0pt,842pt,595pt,0pt);"}
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:236.85pt;left:709.24pt;z-index:246;"} d
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:102.64pt;z-index:10;"} M
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:7;letter-spacing:.001em;"}
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:9;"} R
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:244.36pt;z-index:80;letter-spacing:.001em;"} Effect of endianess
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:157.89pt;left:122.08pt;z-index:145;"}
%span.fmt-141 *
The ARM can be set up to access its data in either little or big
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:179.37pt;left:146.32pt;z-index:160;letter-spacing:.001em;"} endian format.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:208.17pt;left:122.08pt;z-index:175;letter-spacing:-.002em;"}
%span.fmt-141 *
Little endian:
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:236.85pt;left:160.96pt;z-index:245;letter-spacing:-.002em;"}
• Least significant byte of a word is stored in
%span.fmt-63 b
%span.fmt-63 i
%span.fmt-63 t
%span.fmt-63 s
%span.fmt-63
%span.fmt-63 0
%span.fmt-63 -
%span.fmt-63 7
= succeed "of" do
%span.fmt-63
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:258.33pt;left:180.4pt;z-index:252;"} word.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:287.01pt;left:122.08pt;z-index:264;letter-spacing:-.002em;"}
%span.fmt-141 *
Big endian:
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:315.69pt;left:160.96pt;z-index:328;letter-spacing:-.002em;"}
• Least significant byte of a word is stored in
%span.fmt-63 b
%span.fmt-63 i
%span.fmt-63 t
%span.fmt-63 s
%span.fmt-63
%span.fmt-63 2
%span.fmt-63 4
%span.fmt-63 -
%span.fmt-63 3
%span.fmt-63 1
= succeed "of" do
%span.fmt-63
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:337.17pt;left:180.4pt;z-index:343;"} addressed word.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:365.85pt;left:122.08pt;z-index:411;"}
%span.fmt-141 *
This has no real relevance unless data is stored as words and then
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:387.33pt;left:146.32pt;z-index:469;"} accessed in smaller sized quantities (halfwords or bytes).
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:416.01pt;left:160.96pt;z-index:536;letter-spacing:-.002em;"} • Which byte / halfword is accessed will depend on the endianess of
%span.fmt-141{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:437.49pt;left:180.4pt;z-index:556;"} the system involved.
%img{:alt => "Image_530_0", :src => "./target/7411ebe8c009fe014a242380fa9c7f7d.png", :style => "position:absolute;left:641.92pt;top:505.04pt;width:72.5992pt;height:68.28pt;z-index:61;"}/
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:113.2pt;z-index:56;"} Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:470.92pt;z-index:73;"} x
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%div{:style => "position:absolute;top:411.33pt;left:717.88pt;z-index:85;"} d
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%div{:style => "position:absolute;top:411.33pt;left:734.44pt;z-index:87;"} a
%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:240.16pt;z-index:72;letter-spacing:.001em;"} Endianess E
%span.fmt-145{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:149.01pt;left:338.8pt;z-index:130;"} r0 = 0x11223344
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%div{:style => "position:absolute;top:201.61pt;left:345.28pt;z-index:204;letter-spacing:-.001em;"} 11 22 33 44
%span.fmt-147{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:281.77pt;left:363.76pt;z-index:549;"} STR r0, [r1]
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%span.fmt-144{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:374.17pt;left:120.88pt;z-index:585;letter-spacing:.001em;"} r1 = 0x100
%div{:style => "position:absolute;top:374.17pt;left:198.28pt;z-index:585;letter-spacing:-.001em;"} 11 22 33 44
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%span.fmt-145{:style => "position:relative;left:0pt;top:-1pt;"} M
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%span.fmt-145{:style => "position:relative;left:0pt;top:-1pt;"} o
%span.fmt-145{:style => "position:relative;left:0pt;top:-1pt;"} r
%span.fmt-145{:style => "position:relative;left:0pt;top:-1pt;"} y
%span.fmt-143{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:413.25pt;left:64.7198pt;z-index:565;"} Little-endian
%div{:style => "position:absolute;top:413.25pt;left:357.28pt;z-index:565;letter-spacing:.001em;"}
%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} L
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%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} R
%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} B
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%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} r
%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} 2
%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} ,
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%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} [
%span.fmt-147{:style => "position:relative;left:0pt;top:2pt;"} r
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%div{:style => "position:absolute;top:475.69pt;left:197.92pt;z-index:435;letter-spacing:-.001em;"} 00 00 00 44
%span.fmt-145{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:500.13pt;left:220.12pt;z-index:524;letter-spacing:.001em;"} r2 = 0x44
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:492.52pt;z-index:78;letter-spacing:.001em;"} ample
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%div{:style => "position:absolute;top:353.78pt;left:492.52pt;z-index:328;letter-spacing:.002em;"} 31 24 23 16 15 8 7 0
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%div{:style => "position:absolute;top:475.57pt;left:506.56pt;z-index:511;letter-spacing:-.001em;"} 00 00 00 11
%span.fmt-145{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:500.97pt;left:525.64pt;z-index:534;letter-spacing:.001em;"} r2 = 0x11
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%div{:style => "position:absolute;top:375.01pt;left:658.48pt;z-index:579;letter-spacing:.001em;"} r1 = 0x100
%span.fmt-143{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:411.33pt;left:662.56pt;z-index:84;letter-spacing:.001em;"} Big-en
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%div{:style => "position:absolute;top:411.33pt;left:728.92pt;z-index:86;letter-spacing:.001em;"} i
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%div{:style => "position:absolute;top:411.33pt;left:744.4pt;z-index:88;"} n
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%b Page 52
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:70.3622pt;left:353.44pt;z-index:68;letter-spacing:.001em;"} Quiz #4
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:131;"}
%span.fmt-148 *
Write a segment of code that add together elements x to x+(n-1
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:202;"} array, where the element x=0 is the first element of the array.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:205.17pt;left:98.4397pt;z-index:257;letter-spacing:-.001em;"}
%span.fmt-148 *
Each element of the array is word sized (ie. 32 bits).
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:233.97pt;left:98.4395pt;z-index:305;"}
%span.fmt-148 *
The segment should use post-indexed addressing.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:262.65pt;left:98.4404pt;z-index:360;"}
%span.fmt-148 *
At the start of your segments, you should assume that:
%span.fmt-148{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:455;letter-spacing:-.003em;"} • r0 points to the start of the array.
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%div{:style => "position:absolute;top:320.01pt;left:137.32pt;z-index:404;letter-spacing:-.012em;"} • r1 = x
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%div{:style => "position:absolute;top:348.69pt;left:137.32pt;z-index:411;letter-spacing:-.012em;"} • r2 = n
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%div{:style => "position:absolute;top:491.07pt;left:368.44pt;z-index:468;letter-spacing:-.002em;"} r0
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 52
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%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
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%div{:style => "position:absolute;top:70.3622pt;left:184.36pt;z-index:85;letter-spacing:.001em;"} Quiz #4 - Sample Solution
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%div{:style => "position:absolute;top:178.93pt;left:112.6pt;z-index:139;"} ADD r0, r0, r1, LSL#2
%div{:style => "position:absolute;top:178.93pt;left:399.16pt;z-index:139;"} ; Set r0 to address of element x
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%div{:style => "position:absolute;top:203.89pt;left:112.6pt;z-index:194;"} ADD r2, r0, r2, LSL#2
%div{:style => "position:absolute;top:203.89pt;left:399.16pt;z-index:194;"} ; Set r2 to address of element n+1
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%div{:style => "position:absolute;top:228.01pt;left:112.6pt;z-index:224;"} MOV r1, #0
%div{:style => "position:absolute;top:228.01pt;left:399.16pt;z-index:224;"} ; Initialise counter
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%div{:style => "position:absolute;top:252.13pt;left:88.359pt;z-index:228;"} loop
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%div{:style => "position:absolute;top:276.25pt;left:112.6pt;z-index:277;"} LDR r3, [r0], #4
%div{:style => "position:absolute;top:276.25pt;left:399.16pt;z-index:277;"} ; Access element and move to next
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%div{:style => "position:absolute;top:300.25pt;left:112.6pt;z-index:316;letter-spacing:.001em;"} ADD r1, r1, r3
%div{:style => "position:absolute;top:300.25pt;left:399.16pt;z-index:316;letter-spacing:.001em;"} ; Add contents to counter
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%div{:style => "position:absolute;top:324.37pt;left:112.6pt;z-index:356;"} CMP r0, r2
%div{:style => "position:absolute;top:324.37pt;left:399.16pt;z-index:356;"} ; Have we reached element x+n?
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%div{:style => "position:absolute;top:348.49pt;left:112.6pt;z-index:385;"} BLT loop
%div{:style => "position:absolute;top:348.49pt;left:399.15pt;z-index:385;"} ; If not - repeat for
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:370.69pt;left:399.16pt;z-index:399;"} ;
%div{:style => "position:absolute;top:370.69pt;left:487pt;z-index:399;letter-spacing:.001em;"} next element
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%div{:style => "position:absolute;top:392.77pt;left:112.6pt;z-index:428;"} ; on exit sum contained in r1
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%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:81.0397pt;z-index:58;"} ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:209.8pt;z-index:88;letter-spacing:.001em;"} Block Data Transfer (1)
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%span.fmt-156 *
The Load and Store Multiple instructions (LDM / STM) allow betweeen
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:943;"} 1 and 16 registers to be transferred to or from memory.
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The transferred registers can be either:
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:1039;letter-spacing:-.002em;"} • Any subset of the current bank of registers (default).
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%div{:style => "position:absolute;top:262.65pt;left:137.32pt;z-index:1108;letter-spacing:-.002em;"} • Any subset of the user mode bank of registers when in a priviledged
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mode (postfix instruction with a
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%div{:style => "position:absolute;top:345.25pt;left:169.6pt;z-index:174;letter-spacing:-.001em;"} Cond 1 0 0 P U S W L Rn
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%span{:style => "white-space:pre;"}
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:58;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:209.8pt;z-index:84;letter-spacing:.001em;"} Block Data Transfer (2)
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Base register used to determine where memory access should occur.
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%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:221;letter-spacing:-.002em;"} • 4 different addressing modes allow increment and decrement inclusive o
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:331;letter-spacing:-.002em;"} • Base register can be optionally updated following the transfer (by
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appending it with an
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.
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%div{:style => "position:absolute;top:284.13pt;left:137.32pt;z-index:424;letter-spacing:-.002em;"} • Lowest register number is always transferred to/from lowest memory
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%div{:style => "position:absolute;top:305.61pt;left:156.76pt;z-index:442;letter-spacing:-.001em;"} location accessed.
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These instructions are very efficient for
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%div{:style => "position:absolute;top:362.97pt;left:137.32pt;z-index:513;letter-spacing:-.004em;"} • Saving and restoring context
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%div{:style => "position:absolute;top:391.65pt;left:176.2pt;z-index:556;letter-spacing:-.001em;"} For this useful to view memory as a stack.
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%div{:style => "position:absolute;top:420.33pt;left:137.32pt;z-index:598;letter-spacing:-.003em;"} • Moving large blocks of data around memory
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%div{:style => "position:absolute;top:449.01pt;left:176.2pt;z-index:671;"} For this useful to directly represent functionality of the instructions.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:359.8pt;z-index:67;letter-spacing:.001em;"} Stacks
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A stack is an area of memory which grows as new data is “pushed” onto
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:196;letter-spacing:.001em;"} the “top” of it, and shrinks as data is “popped” off the top.
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Two pointers define the current limits of the stack.
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:265;letter-spacing:-.007em;"} • A base pointer
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%div{:style => "position:absolute;top:262.65pt;left:176.2pt;z-index:329;letter-spacing:-.001em;"} used to point to the “bottom” of the stack (the first location).
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:345;letter-spacing:-.007em;"} • A stack pointer
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%div{:style => "position:absolute;top:320.01pt;left:176.2pt;z-index:391;letter-spacing:-.001em;"} used to point the current “top” of the stack.
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%div{:style => "position:absolute;top:358.21pt;left:278.92pt;z-index:408;"} PUSH
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%div{:style => "position:absolute;top:70.3622pt;left:273.64pt;z-index:76;letter-spacing:.001em;"} Stack Operation
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%div{:style => "position:absolute;top:155.01pt;left:98.4391pt;z-index:144;letter-spacing:-.006em;"}
%span.fmt-162 *
Traditionally, a stack grows down in memory, with the last “ pushed”
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:213;"} value at the lowest address. The ARM also supports ascending stacks,
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%div{:style => "position:absolute;top:197.97pt;left:122.68pt;z-index:264;"} where the stack structure grows up through memory.
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%span.fmt-162 *
The value of the stack pointer can either:
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%div{:style => "position:absolute;top:255.45pt;left:137.32pt;z-index:355;letter-spacing:-.003em;"} • Point to the last occupied address (Full stack)
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%div{:style => "position:absolute;top:284.13pt;left:176.2pt;z-index:406;letter-spacing:-.001em;"} and so needs pre-decrementing (ie before the push)
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%div{:style => "position:absolute;top:312.81pt;left:137.32pt;z-index:455;letter-spacing:-.003em;"} • Point to the next occupied address (Empty stack)
%span.fmt-162{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:341.49pt;left:176.2pt;z-index:506;letter-spacing:-.001em;"} and so needs post-decrementing (ie after the push)
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%div{:style => "position:absolute;top:370.17pt;left:98.4416pt;z-index:576;"}
%span.fmt-162 *
The stack type to be used is given by the postfix to the instruction:
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%div{:style => "position:absolute;top:398.85pt;left:137.32pt;z-index:614;letter-spacing:-.003em;"} • STMFD / LDMFD : Full Descending stack
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%div{:style => "position:absolute;top:427.53pt;left:137.32pt;z-index:652;letter-spacing:-.003em;"} • STMFA / LDMFA : Full Ascending stack.
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%div{:style => "position:absolute;top:456.21pt;left:137.32pt;z-index:691;letter-spacing:-.003em;"} • STMED / LDMED : Empty Descending stack
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%div{:style => "position:absolute;top:485.01pt;left:137.32pt;z-index:729;letter-spacing:-.003em;"} • STMEA / LDMEA : Empty Ascending stack
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%span.fmt-162 *
Note: ARM Compiler will always use a Full descending stack.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:143.52pt;left:129.64pt;z-index:97;letter-spacing:-.001em;"} r0,r1,r3-r5
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%div{:style => "position:absolute;top:404.64pt;left:166.12pt;z-index:112;letter-spacing:-.002em;"} r1
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:29;letter-spacing:.001em;"} struction Set - A
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%div{:style => "position:absolute;top:70.3622pt;left:201.28pt;z-index:83;letter-spacing:.001em;"} Stacks and Subroutines
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%span.fmt-165 *
One use of stacks is to create temporary register workspace for
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:220;"} subroutines. Any registers that are needed can be pushed onto the stack
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%div{:style => "position:absolute;top:197.97pt;left:122.68pt;z-index:292;letter-spacing:.001em;"} at the start of the subroutine and popped off again at the end so as to
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%div{:style => "position:absolute;top:219.45pt;left:122.68pt;z-index:334;"} restore them before return to the caller :
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%div{:style => "position:absolute;top:247.09pt;left:98.4387pt;z-index:377;"} STMFD sp!,{r0-r12, lr}
%div{:style => "position:absolute;top:247.09pt;left:409.24pt;z-index:377;"} ; stack all registers
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%div{:style => "position:absolute;top:271.33pt;left:98.4391pt;z-index:409;"} ........
%div{:style => "position:absolute;top:271.33pt;left:409.24pt;z-index:409;"} ; and the return address
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%div{:style => "position:absolute;top:295.57pt;left:98.4396pt;z-index:417;"} ........
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%div{:style => "position:absolute;top:319.81pt;left:98.4396pt;z-index:463;"} LDMFD sp!,{r0-r12, pc}
%div{:style => "position:absolute;top:319.81pt;left:409.24pt;z-index:463;"} ; load all the registers
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%div{:style => "position:absolute;top:344.05pt;left:409.24pt;z-index:489;letter-spacing:.001em;"} ; and return automatically
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%span.fmt-165 *
See the chapter on the ARM Procedure Call Standard in the SDT
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%div{:style => "position:absolute;top:390.93pt;left:122.68pt;z-index:614;"} Reference Manual for further details of register usage within
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%div{:style => "position:absolute;top:412.41pt;left:122.68pt;z-index:626;letter-spacing:.001em;"} subroutines.
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%span.fmt-165 *
If the pop instruction also had the S bit set (using ^) then the transfer
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%div{:style => "position:absolute;top:462.57pt;left:122.68pt;z-index:773;letter-spacing:.001em;"} of the PC when in a priviledged mode would also cause the SPSR to be
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%div{:style => "position:absolute;top:484.05pt;left:122.68pt;z-index:826;letter-spacing:.001em;"} copied into the CPSR (see exception handling module).
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:58;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:155.01pt;left:735.16pt;z-index:175;"} o
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%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
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%div{:style => "position:absolute;top:49.3622pt;left:222.88pt;z-index:84;letter-spacing:.001em;"} Direct functionality of
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%div{:style => "position:absolute;top:91.242pt;left:238.96pt;z-index:103;letter-spacing:.001em;"} Block Data Transfer
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%span.fmt-168 *
When LDM / STM are not being used to implement stacks, it is clearer t
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:233;"} specify exactly what functionality of the instruction is:
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%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:308;letter-spacing:-.002em;"} • i.e. specify whether to increment / decrement the base pointer, before or
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%div{:style => "position:absolute;top:226.77pt;left:156.76pt;z-index:332;letter-spacing:-.001em;"} after the memory access.
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%span.fmt-168 *
In order to do this, LDM / STM support a further syntax in addition to
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%div{:style => "position:absolute;top:276.93pt;left:122.68pt;z-index:419;"} the stack one:
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%div{:style => "position:absolute;top:305.61pt;left:137.32pt;z-index:451;letter-spacing:-.003em;"} • STMIA / LDMIA : Increment After
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%div{:style => "position:absolute;top:334.29pt;left:137.32pt;z-index:484;letter-spacing:-.003em;"} • STMIB / LDMIB : Increment Before
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%div{:style => "position:absolute;top:362.97pt;left:137.32pt;z-index:516;letter-spacing:-.003em;"} • STMDA / LDMDA : Decrement After
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%div{:style => "position:absolute;top:391.65pt;left:137.32pt;z-index:549;letter-spacing:-.003em;"} • STMDB / LDMDB : Decrement Before
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:224.08pt;z-index:80;letter-spacing:.001em;"} Example: Block Copy
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%div{:style => "position:absolute;top:161.85pt;left:106pt;z-index:149;letter-spacing:-.002em;"} • Copy a block of memory, which is an exact multiple of 12 words long
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%div{:style => "position:absolute;top:183.33pt;left:125.44pt;z-index:222;"} from the location pointed to by r12 to the location pointed to by r13. r1
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%div{:style => "position:absolute;top:204.81pt;left:125.44pt;z-index:264;"} points to the end of block to be copied.
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:256.69pt;left:67.1193pt;z-index:308;"} ; r12 points to the start of the source data
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:280.93pt;left:67.119pt;z-index:350;letter-spacing:.001em;"} ; r14 points to the end of the source data
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:305.17pt;left:67.1188pt;z-index:399;letter-spacing:.001em;"} ; r13 points to the start of the destination data
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%div{:style => "position:absolute;top:329.41pt;left:67.1185pt;z-index:613;letter-spacing:-.002em;"} loop LDMIA r12!, {r0-r11} ; load 48 bytes
%div{:style => "position:absolute;top:329.41pt;left:587.92pt;z-index:613;letter-spacing:.002em;"}
%span.fmt-171{:style => "position:relative;left:0pt;top:-9pt;"} r
%span.fmt-171{:style => "position:relative;left:0pt;top:-9pt;"} 1
%span.fmt-171{:style => "position:relative;left:0pt;top:-9pt;"} 3
%img{:alt => "__rendered_path__610", :src => "./target/cd9671188018a98ac51bd815ec2a0097.png", :style => "position:absolute;left:625.84pt;top:325.52pt;width:14pt;height:9pt;z-index:610;"}/
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%div{:style => "position:absolute;top:353.65pt;left:144.88pt;z-index:616;letter-spacing:.002em;"} STMIA r13!, {r0-r11} ; and store them
%div{:style => "position:absolute;top:353.65pt;left:587.92pt;z-index:616;letter-spacing:.002em;"}
%span.fmt-171{:style => "position:relative;left:0pt;top:3pt;"} r
%span.fmt-171{:style => "position:relative;left:0pt;top:3pt;"} 1
%span.fmt-171{:style => "position:relative;left:0pt;top:3pt;"} 4
%img{:alt => "__rendered_path__620", :src => "./target/e9e7ac0c3099686888c76186a805f76f.png", :style => "position:absolute;left:625.84pt;top:362.84pt;width:14pt;height:9pt;z-index:620;"}/
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%div{:style => "position:absolute;top:377.89pt;left:144.88pt;z-index:502;"} CMP
%div{:style => "position:absolute;top:377.89pt;left:222.52pt;z-index:502;"} r12, r14
%div{:style => "position:absolute;top:377.89pt;left:377.92pt;z-index:502;"} ; check for the end
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%div{:style => "position:absolute;top:402.13pt;left:144.88pt;z-index:530;"} BNE
%div{:style => "position:absolute;top:402.13pt;left:222.52pt;z-index:530;"} loop
%div{:style => "position:absolute;top:402.13pt;left:377.92pt;z-index:530;"} ; and loop until done
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%div{:style => "position:absolute;top:457.65pt;left:106pt;z-index:619;letter-spacing:-.003em;"} • This loop transfers 48 bytes in 31 cycles
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%span.fmt-171{:style => "position:relative;left:0pt;top:-13pt;"} r
%span.fmt-171{:style => "position:relative;left:0pt;top:-13pt;"} 1
%span.fmt-171{:style => "position:relative;left:0pt;top:-13pt;"} 2
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%div{:style => "position:absolute;top:486.45pt;left:106pt;z-index:601;letter-spacing:-.004em;"} • Over 50 Mbytes/sec at 33 MHz
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:56;"} The ARM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:364.09pt;left:729.16pt;z-index:638;"} Increasing
%img{:alt => "__rendered_path__602", :src => "./target/9e7e30c89270884958a27fbc9b696d1a.png", :style => "position:absolute;left:642.64pt;top:308.68pt;width:64pt;height:22pt;z-index:602;"}/
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%span.fmt-171{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:377.77pt;left:734.32pt;z-index:644;letter-spacing:.002em;"} Memory
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%div{:style => "position:absolute;top:552.8pt;left:759.16pt;z-index:58;letter-spacing:-.002em;"} 61
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%div{:style => "position:absolute;top:384.57pt;left:688.84pt;z-index:323;"} t
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:74.0797pt;z-index:6;"} e
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:84.7597pt;z-index:8;"} A
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:5;"} Th
%span.fmt-0{:style => "white-space:pre;"}
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%span.fmt-1{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:70.3622pt;left:353.44pt;z-index:68;letter-spacing:.001em;"} Quiz #5
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:155.01pt;left:98.44pt;z-index:135;"}
%span.fmt-172 *
The contents of registers r0 to r6 need to be swapped around thus:
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:183.69pt;left:137.32pt;z-index:152;letter-spacing:-.006em;"} • r0 moved into r3
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:212.49pt;left:137.32pt;z-index:169;letter-spacing:-.006em;"} • r1 moved into r4
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:241.17pt;left:137.32pt;z-index:186;letter-spacing:-.006em;"} • r2 moved into r6
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:203;letter-spacing:-.006em;"} • r3 moved into r5
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:298.53pt;left:137.32pt;z-index:220;letter-spacing:-.006em;"} • r4 moved into r0
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:327.21pt;left:137.32pt;z-index:237;letter-spacing:-.006em;"} • r5 moved into r1
%span.fmt-172{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:355.89pt;left:137.32pt;z-index:254;letter-spacing:-.006em;"} • r6 moved into r2
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:384.57pt;left:98.4397pt;z-index:322;"}
%span.fmt-172 *
Write a segment of code that uses full descending stack operations
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:406.05pt;left:122.68pt;z-index:393;"} carry this out, and hence requires no use of any other registers for
%span{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:427.53pt;left:122.68pt;z-index:411;"} temporary storage.
%span.fmt-0{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
%img{:alt => "__rendered_path__1", :src => "./target/d357b72a53ec0c37cd3be24596b5a36e.png", :style => "position:absolute;left:56.56pt;top:537.84pt;width:719pt;height:2.3pt;z-index:1;"}/
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%div{:style => "position:absolute;top:384.57pt;left:695.44pt;z-index:325;"} o
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%div{:style => "position:absolute;top:70.3622pt;left:404.32pt;z-index:73;"} m
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%div{:style => "position:absolute;top:70.3622pt;left:438.76pt;z-index:74;letter-spacing:.001em;"} p
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%div{:style => "position:absolute;top:70.3622pt;left:531.4pt;z-index:79;letter-spacing:.001em;"} o
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%div{:style => "position:absolute;top:70.3622pt;left:565.84pt;z-index:81;letter-spacing:.001em;"} u
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%div{:style => "position:absolute;top:70.3622pt;left:602.44pt;z-index:83;letter-spacing:.001em;"} i
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%div{:style => "position:absolute;top:552.8pt;left:120.28pt;z-index:13;letter-spacing:.001em;"} n
%span.fmt-174{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:225.69pt;left:79.12pt;z-index:208;letter-spacing:.001em;"} Old SP
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%div{:style => "position:absolute;top:354.13pt;left:93.5197pt;z-index:229;letter-spacing:-.001em;"} SP
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:12;letter-spacing:-.001em;"} The ARM I
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%div{:style => "position:absolute;top:70.3622pt;left:184.36pt;z-index:72;letter-spacing:.001em;"} Quiz #5 - Sa
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%div{:style => "position:absolute;top:174.12pt;left:132.04pt;z-index:112;letter-spacing:-.001em;"} STMFD sp!,
%div{:style => "position:absolute;top:174.12pt;left:285.16pt;z-index:112;letter-spacing:-.001em;"} LDMFD sp!,
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%div{:style => "position:absolute;top:189.96pt;left:145.24pt;z-index:122;letter-spacing:-.001em;"} {r0-r6}
%div{:style => "position:absolute;top:189.96pt;left:285.16pt;z-index:122;letter-spacing:-.001em;"} {r3,r4,r6}
%img{:alt => "__rendered_path__209", :src => "./target/90f11b2ea0d28d15347a24d0471bbb4e.png", :style => "position:absolute;left:145.6pt;top:221.6pt;width:58pt;height:18pt;z-index:209;"}/
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%span.fmt-175{:style => "white-space:pre;"}
%div{:style => "position:absolute;top:242.22pt;left:167.92pt;z-index:254;letter-spacing:-.002em;"} r6
%div{:style => "position:absolute;top:242.22pt;left:322.12pt;z-index:254;letter-spacing:-.002em;"} r6
%img{:alt => "__rendered_path__209", :src => "./target/90f11b2ea0d28d15347a24d0471bbb4e.png", :style => "position:absolute;left:145.6pt;top:240.32pt;width:58pt;height:18pt;z-index:209;"}/
%img{:alt => "__rendered_path__237", :src => "./target/21ee112d2e0dee2376bd25a73de1e5f3.png", :style => "position:absolute;left:299.8pt;top:221.6pt;width:59pt;height:18pt;z-index:237;"}/
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%div{:style => "position:absolute;top:261.06pt;left:167.32pt;z-index:243;letter-spacing:-.002em;"} r5
%div{:style => "position:absolute;top:261.06pt;left:321.52pt;z-index:243;letter-spacing:-.002em;"} r5
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%div{:style => "position:absolute;top:281.22pt;left:167.32pt;z-index:245;letter-spacing:-.002em;"} r4
%div{:style => "position:absolute;top:281.22pt;left:321.52pt;z-index:245;letter-spacing:-.002em;"} r4
%img{:alt => "__rendered_path__211", :src => "./target/096960cdde5753422fdb032f89b38e3c.png", :style => "position:absolute;left:145.6pt;top:277.64pt;width:58pt;height:18pt;z-index:211;"}/
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%div{:style => "position:absolute;top:301.38pt;left:167.32pt;z-index:256;letter-spacing:-.002em;"} r3
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%span.fmt-176{:style => "position:relative;left:0pt;top:-2pt;"} S
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:56;letter-spacing:-.001em;"} struction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:174.13pt;left:620.44pt;z-index:174;letter-spacing:-.001em;"} LDMFD sp!,
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%div{:style => "position:absolute;top:49.3629pt;left:228.4pt;z-index:349;letter-spacing:.001em;"} Swap and Swap Byte
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%div{:style => "position:absolute;top:91.2427pt;left:311.32pt;z-index:361;letter-spacing:.001em;"} Instructions
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%span.fmt-177 *
Atomic operation of a memory read followed by a memory wri
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%div{:style => "position:absolute;top:183.69pt;left:171.52pt;z-index:181;"} which moves byte or word quantities between registers and
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%div{:style => "position:absolute;top:205.17pt;left:171.52pt;z-index:189;letter-spacing:.001em;"} memory.
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%span.fmt-177 *
Syntax:
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%div{:style => "position:absolute;top:262.65pt;left:186.16pt;z-index:225;letter-spacing:-.004em;"} • SWP{&lt;cond&gt;}{B} Rd, Rm, [Rn]
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%div{:style => "position:absolute;top:431.52pt;left:214.96pt;z-index:373;"} Rm
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%span{:style => "position:relative;left:0pt;top:-4pt;"} d
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%span.fmt-177 *
Thus to implement an actual swap of contents make Rd = Rm.
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%span.fmt-177 *
The compiler cannot produce this instruction.
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%div{:style => "position:absolute;top:552.8pt;left:127.96pt;z-index:56;letter-spacing:-.001em;"} struction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:200.32pt;z-index:85;letter-spacing:.001em;"} Software Interrupt (SWI)
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%div{:style => "position:absolute;top:236.01pt;left:234.4pt;z-index:730;letter-spacing:.001em;"} Condition Field
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%span.fmt-179 *
In effect, a SWI is a user-defined instruction.
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%span.fmt-179 *
It causes an exception trap to the SWI hardware vector (thus causing a
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%div{:style => "position:absolute;top:334.05pt;left:122.68pt;z-index:278;"} change to supervisor mode, plus the associated state saving), thus causin
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%div{:style => "position:absolute;top:355.53pt;left:122.68pt;z-index:319;"} the SWI exception handler to be called.
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%span.fmt-179 *
The handler can then examine the comment field of the instruction to
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%div{:style => "position:absolute;top:405.69pt;left:122.68pt;z-index:430;letter-spacing:.001em;"} decide what operation has been requested.
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%span.fmt-179 *
By making use of the SWI mechansim, an operating system can
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%div{:style => "position:absolute;top:455.85pt;left:122.68pt;z-index:562;"} implement a set of privileged operations which applications running in
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%div{:style => "position:absolute;top:477.33pt;left:122.68pt;z-index:584;"} user mode can request.
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%span.fmt-179 *
See Exception Handling Module for further details.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:183.04pt;z-index:86;letter-spacing:.001em;"} PSR Transfer Instructions
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%span.fmt-183 *
MRS and MSR allow contents of CPSR/SPSR to be transferred
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:208;"} appropriate status register to a general purpose register.
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%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:271;letter-spacing:-.002em;"} • All of status register, or just the flags, can be transferred.
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%span.fmt-183 *
Syntax:
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%span.fmt-183 •
MRS{&lt;cond&gt;} Rd,&lt;psr&gt;
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%span.fmt-183 •
MSR{&lt;cond&gt;} &lt;psr&gt;,Rm
%div{:style => "position:absolute;top:290.01pt;left:487pt;z-index:345;letter-spacing:-.001em;"} ; &lt;psr&gt; = Rm
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%span.fmt-183 •
MSR{&lt;cond&gt;} &lt;psrf&gt;,Rm
%div{:style => "position:absolute;top:318.69pt;left:487pt;z-index:380;letter-spacing:-.001em;"} ; &lt;psrf&gt; = Rm
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%div{:style => "position:absolute;top:348.69pt;left:122.68pt;z-index:385;"} where
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%span.fmt-183 •
\&lt;psr&gt; = CPSR, CPSR_all, SPSR or SPSR_all
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%span.fmt-183 •
\&lt;psrf&gt; = CPSR_flg or SPSR_flg
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%span.fmt-183 *
Also an immediate form
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%span.fmt-183 •
MSR{&lt;cond&gt;} &lt;psrf&gt;,#Immediate
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%div{:style => "position:absolute;top:492.21pt;left:137.32pt;z-index:569;letter-spacing:-.002em;"} • This immediate must be a 32-bit immediate, of which the 4
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%div{:style => "position:absolute;top:513.69pt;left:156.76pt;z-index:620;"} most significant bits are written to the flag bits.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:231.76pt;z-index:78;letter-spacing:.001em;"} Using MRS and MSR
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Currently reserved bits, may be used in future, therefore:
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%div{:style => "position:absolute;top:183.69pt;left:138.4pt;z-index:178;letter-spacing:-.003em;"} • they must be preserved when altering PSR
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%div{:style => "position:absolute;top:212.49pt;left:138.4pt;z-index:248;letter-spacing:-.002em;"} • the value they return must not be relied upon when testing other bits.
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%span.fmt-185 *
Thus read-modify-write strategy must be followed when modifying a
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%div{:style => "position:absolute;top:348.69pt;left:122.68pt;z-index:321;letter-spacing:.001em;"} PSR:
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%div{:style => "position:absolute;top:377.37pt;left:138.4pt;z-index:356;letter-spacing:-.003em;"} • Transfer PSR to register using MRS
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%div{:style => "position:absolute;top:406.05pt;left:138.4pt;z-index:377;letter-spacing:-.005em;"} • Modify relevant bits
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%div{:style => "position:absolute;top:434.73pt;left:138.4pt;z-index:422;letter-spacing:-.003em;"} • Transfer updated value back to PSR using MSR
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Note:
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%div{:style => "position:absolute;top:492.21pt;left:138.4pt;z-index:491;letter-spacing:-.002em;"} • In User Mode, all bits can be read but only the flag bits can
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%div{:style => "position:absolute;top:70.3622pt;left:291.88pt;z-index:73;letter-spacing:.001em;"} Coprocessors
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The ARM architecture supports 16 coprocessors
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%span.fmt-189 *
Each coprocessor instruction set occupies part of the ARM instruction
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%div{:style => "position:absolute;top:205.17pt;left:122.68pt;z-index:194;letter-spacing:.001em;"} set.
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%span.fmt-189 *
There are three types of coprocessor instruction
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%div{:style => "position:absolute;top:262.65pt;left:137.32pt;z-index:271;letter-spacing:-.004em;"} • Coprocessor data processing
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:316;letter-spacing:-.003em;"} • Coprocessor (to/from ARM) register transfers
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%div{:style => "position:absolute;top:320.01pt;left:137.32pt;z-index:377;letter-spacing:-.002em;"} • Coprocessor memory transfers (load and store to/from memory)
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%span.fmt-189 *
Assembler macros can be used to transform custom coprocessor
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%div{:style => "position:absolute;top:370.17pt;left:122.68pt;z-index:506;letter-spacing:.001em;"} mneumonics into the generic mneumonics understood by the processor.
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%span.fmt-189 *
A coprocessor may be implemented
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%div{:style => "position:absolute;top:427.53pt;left:137.32pt;z-index:552;letter-spacing:-.008em;"} • in hardware
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%div{:style => "position:absolute;top:456.21pt;left:137.32pt;z-index:606;letter-spacing:-.002em;"} • in software (via the undefined instruction exception)
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%div{:style => "position:absolute;top:485.01pt;left:137.32pt;z-index:663;letter-spacing:-.002em;"} • in both (common cases in hardware, the rest in software)
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:145.24pt;z-index:88;letter-spacing:.001em;"} Coprocessor Data Processing
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%span.fmt-191 *
This instruction initiates a coprocessor operation
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%span.fmt-191 *
The operation is performed only on internal coprocessor state
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%div{:style => "position:absolute;top:212.49pt;left:138.4pt;z-index:273;letter-spacing:-.002em;"} • For example, a Floating point multiply, which multiplies the contents o
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%div{:style => "position:absolute;top:233.97pt;left:157.84pt;z-index:330;"} two registers and stores the result in a third register
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%span.fmt-191 *
Syntax:
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%span.fmt-193 •
CDP{&lt;cond&gt;} &lt;cp_num&gt;,&lt;opc_1&gt;,CRd,CRn,CRm,{&lt;opc_2&gt;}
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%div{:style => "position:absolute;top:383.32pt;left:133.72pt;z-index:635;"} Cond 1 1 1 0 opc_1 CRn CRd cp_num opc_2 0 CRm
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%div{:style => "position:absolute;top:427.62pt;left:435.04pt;z-index:539;letter-spacing:.001em;"} Destination Register
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%div{:style => "position:absolute;top:446.34pt;left:482.08pt;z-index:532;letter-spacing:.001em;"} Source Registers
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%div{:style => "position:absolute;top:456.66pt;left:293.92pt;z-index:575;letter-spacing:.001em;"} Opcode
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%div{:style => "position:absolute;top:471.3pt;left:143.2pt;z-index:564;letter-spacing:.001em;"} Condition Code Specifier
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:56;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:552.8pt;left:58.7197pt;z-index:10;letter-spacing:-.002em;"} The ARM
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%div{:style => "position:absolute;top:49.3622pt;left:219.64pt;z-index:82;letter-spacing:.001em;"} Coprocessor Register
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%div{:style => "position:absolute;top:91.242pt;left:334pt;z-index:91;letter-spacing:.001em;"} Transfers
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%div{:style => "position:absolute;top:155.01pt;left:122.68pt;z-index:151;"} These two instructions move data between ARM registers and
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:172;letter-spacing:-.001em;"} coprocessor registers
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%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:212;letter-spacing:-.003em;"} • MRC : Move to Register from Coprocessor
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:252;letter-spacing:-.003em;"} • MCR : Move to Coprocessor from Register
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%div{:style => "position:absolute;top:262.65pt;left:122.68pt;z-index:320;"} An operation may also be performed on the data as it is transferred
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%div{:style => "position:absolute;top:291.33pt;left:137.32pt;z-index:388;letter-spacing:-.002em;"} • For example a Floating Point Convert to Integer instruction can be
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%div{:style => "position:absolute;top:312.81pt;left:156.76pt;z-index:457;letter-spacing:-.001em;"} implemented as a register transfer to ARM that also converts the data
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%div{:style => "position:absolute;top:334.29pt;left:156.76pt;z-index:502;"} from floating point format to integer format.
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%div{:style => "position:absolute;top:362.97pt;left:122.68pt;z-index:509;"} Syntax
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%span.fmt-200 •
\&lt;MRC|MCR&gt;{&lt;cond&gt;} &lt;cp_num&gt;,&lt;opc_1&gt;,Rd,CRn,CRm,&lt;opc_2&gt;
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%div{:style => "position:absolute;top:414.38pt;left:121.72pt;z-index:657;letter-spacing:.002em;"} 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11
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%div{:style => "position:absolute;top:432.67pt;left:132.16pt;z-index:865;"} Cond 1 1 1 0 opc_1 L CRn Rd cp_num opc_2 1 CRm
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%div{:style => "position:absolute;top:478.16pt;left:407.32pt;z-index:735;letter-spacing:-.001em;"} ARM Source/Dest Register
%div{:style => "position:absolute;top:478.16pt;left:588.4pt;z-index:735;"} Opcode
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%div{:style => "position:absolute;top:552.8pt;left:116.68pt;z-index:58;"} Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:49.3622pt;left:223pt;z-index:80;letter-spacing:.001em;"} Coprocessor Memory
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%div{:style => "position:absolute;top:91.242pt;left:304.84pt;z-index:93;letter-spacing:.001em;"} Transfers (1)
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%span.fmt-205 *
Load from memory to coprocessor registers
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%span.fmt-205 *
Store to memory from coprocessor registers.
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%div{:style => "position:absolute;top:282.31pt;left:125.92pt;z-index:522;"} Cond 1 1 0 P U N W L Rn CRd cp_num Offset
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%div{:style => "position:absolute;top:328.04pt;left:414.52pt;z-index:465;letter-spacing:-.002em;"} Source/Dest Register
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%div{:style => "position:absolute;top:345.56pt;left:361.36pt;z-index:346;letter-spacing:-.002em;"} Base Register
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%div{:style => "position:absolute;top:360.2pt;left:316.48pt;z-index:359;letter-spacing:-.002em;"} Load/Store
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%div{:style => "position:absolute;top:378.2pt;left:83.6796pt;z-index:412;letter-spacing:-.003em;"} Condition Code Specifier
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%div{:style => "position:absolute;top:404pt;left:261.88pt;z-index:448;letter-spacing:-.001em;"} Add/Subtract Offset
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%div{:style => "position:absolute;top:49.3622pt;left:223pt;z-index:80;letter-spacing:.001em;"} Coprocessor Memory
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%div{:style => "position:absolute;top:91.242pt;left:304.84pt;z-index:93;letter-spacing:.001em;"} Transfers (2)
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%span.fmt-207 *
Syntax of these is similar to word transfers between ARM and memory:
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%span.fmt-209 •
\&lt;LDC|STC&gt;{&lt;cond&gt;}{&lt;L&gt;} &lt;cp_num&gt;,CRd,&lt;address&gt;
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%div{:style => "position:absolute;top:220.05pt;left:176.2pt;z-index:272;letter-spacing:-.001em;"} PC relative offset generated if possible, else causes an error.
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%span.fmt-209 •
\&lt;LDC|STC&gt;{&lt;cond&gt;}{&lt;L&gt;} &lt;cp_num&gt;,CRd,&lt;[Rn,offset]{!}&gt;
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%div{:style => "position:absolute;top:284.97pt;left:176.2pt;z-index:388;"} Pre-indexed form, with optional writeback of the base register
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%span.fmt-209 •
\&lt;LDC|STC&gt;{&lt;cond&gt;}{&lt;L&gt;} &lt;cp_num&gt;,CRd,&lt;[Rn],offset&gt;
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%div{:style => "position:absolute;top:350.01pt;left:176.2pt;z-index:456;letter-spacing:-.001em;"} Post-indexed form
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%div{:style => "position:absolute;top:407.37pt;left:137.32pt;z-index:530;letter-spacing:-.008em;"} • &lt;L&gt; when present causes a “ long” transfer to be performed (N=1) else
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%div{:style => "position:absolute;top:428.85pt;left:156.76pt;z-index:577;letter-spacing:-.01em;"} causes a “ short” transfer to be performed (N=0).
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%div{:style => "position:absolute;top:457.53pt;left:176.2pt;z-index:618;letter-spacing:-.001em;"} Effect of this is coprocessor dependant.
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%div{:style => "position:absolute;top:552.8pt;left:93.5197pt;z-index:58;"} RM Instruction Set - ARM University Program - V1.0
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%div{:style => "position:absolute;top:70.3622pt;left:353.44pt;z-index:68;letter-spacing:.001em;"} Quiz #6
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%span.fmt-210 *
Write a short code segment that performs a mode change by modifying
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%div{:style => "position:absolute;top:176.49pt;left:122.68pt;z-index:161;letter-spacing:.001em;"} the contents of the CPSR
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%div{:style => "position:absolute;top:205.17pt;left:137.32pt;z-index:231;letter-spacing:-.002em;"} • The mode you should change to is user mode which has the value 0x10.
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%div{:style => "position:absolute;top:233.97pt;left:137.32pt;z-index:296;letter-spacing:-.002em;"} • This assumes that the current mode is a priveleged mode such as
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%div{:style => "position:absolute;top:255.45pt;left:156.76pt;z-index:313;"} supervisor mode.
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%div{:style => "position:absolute;top:284.13pt;left:137.32pt;z-index:385;letter-spacing:-.002em;"} • This would happen for instance when the processor is reset - reset code
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%div{:style => "position:absolute;top:305.61pt;left:156.76pt;z-index:452;"} would be run in supervisor mode which would then need to switch to
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%div{:style => "position:absolute;top:327.09pt;left:156.76pt;z-index:514;"} user mode before calling the main routine in your application.
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%div{:style => "position:absolute;top:355.77pt;left:137.32pt;z-index:575;letter-spacing:-.002em;"} • You will need to use MSR and MRS, plus 2 logical operations.
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%div{:style => "position:absolute;top:70.3622pt;left:184.36pt;z-index:85;letter-spacing:.001em;"} Quiz #6 - Sample Solution
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%span.fmt-214 *
Set up useful constants:
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%div{:style => "position:absolute;top:211.91pt;left:98.4391pt;z-index:147;letter-spacing:-.009em;"} mmask EQU 0x1f
%div{:style => "position:absolute;top:211.91pt;left:409.24pt;z-index:147;letter-spacing:-.002em;"} ; mask to clear mode bits
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%div{:style => "position:absolute;top:239.15pt;left:98.439pt;z-index:176;letter-spacing:-.009em;"} userm EQU 0x10
%div{:style => "position:absolute;top:239.15pt;left:409.24pt;z-index:176;letter-spacing:-.002em;"} ; user mode value
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%span.fmt-214 *
Start off here in supervisor mode.
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%div{:style => "position:absolute;top:325.31pt;left:176.2pt;z-index:250;letter-spacing:-.002em;"} MRS r0, cpsr
%div{:style => "position:absolute;top:325.31pt;left:409.24pt;z-index:250;letter-spacing:-.002em;"} ; take a copy of the CPSR
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%div{:style => "position:absolute;top:352.55pt;left:176.2pt;z-index:289;letter-spacing:-.006em;"} BIC r0,r0,#mmask ; clear the mode bits
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%div{:style => "position:absolute;top:379.79pt;left:176.2pt;z-index:325;letter-spacing:-.007em;"} ORR r0,r0,#userm ; select new mode
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%div{:style => "position:absolute;top:407.03pt;left:176.2pt;z-index:364;letter-spacing:-.002em;"} MSR cpsr, r0
%div{:style => "position:absolute;top:407.03pt;left:409.24pt;z-index:364;letter-spacing:-.002em;"} ; write back the modified
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%div{:style => "position:absolute;top:427.55pt;left:409.24pt;z-index:370;letter-spacing:-.001em;"} ; CPSR
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%span.fmt-214 *
End up here in user mode.
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%div{:style => "position:absolute;top:49.3622pt;left:238.96pt;z-index:81;letter-spacing:.001em;"} Main features of the
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%div{:style => "position:absolute;top:91.242pt;left:237.04pt;z-index:100;letter-spacing:.001em;"} ARM Instruction Set
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%span.fmt-216 *
All instructions are 32 bits long.
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%span.fmt-216 *
Most instructions execute in a single cycle.
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%span.fmt-216 *
Every instruction can be conditionally executed.
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%span.fmt-216 *
A load/store architecture
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%div{:style => "position:absolute;top:269.85pt;left:137.32pt;z-index:307;letter-spacing:-.003em;"} • Data processing instructions act only on registers
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%div{:style => "position:absolute;top:298.53pt;left:176.2pt;z-index:328;letter-spacing:-.001em;"} Three operand format
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%div{:style => "position:absolute;top:327.21pt;left:176.2pt;z-index:385;letter-spacing:-.001em;"} Combined ALU and shifter for high speed bit manipulation
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%div{:style => "position:absolute;top:355.89pt;left:137.32pt;z-index:448;letter-spacing:-.002em;"} • Specific memory access instructions with powerful auto-indexin
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%div{:style => "position:absolute;top:377.37pt;left:156.76pt;z-index:467;"} addressing modes.
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%div{:style => "position:absolute;top:406.05pt;left:176.2pt;z-index:495;letter-spacing:-.001em;"} 32 bit and 8 bit data types
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%div{:style => "position:absolute;top:434.73pt;left:229.6pt;z-index:545;"} and also 16 bit data types on ARM Architecture v4.
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%div{:style => "position:absolute;top:463.41pt;left:176.2pt;z-index:600;letter-spacing:-.001em;"} Flexible multiple register load and store instructions
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%span.fmt-216 *
Instruction set extension via coprocessors
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