Moysan Gabriel f9dba1ac11 machine : Instruction type RISCV_OP		2022-11-15 21:21:24 +01:00
..
decode.rs	Fix decode to allow overflow in certains cases, add a case in test for riscv_lui where imm is negative	2022-11-09 17:31:14 +01:00
machine.rs	machine : Instruction type RISCV_OP	2022-11-15 21:21:24 +01:00
main.rs	simulate some instructions	2022-11-09 17:35:16 +01:00
print.rs	add of the test function for br instructions	2022-11-10 00:47:32 +01:00