634 lines
22 KiB
Rust
634 lines
22 KiB
Rust
use std::{ops::{Add, Sub}, io::Write};
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use super::{decode::{Instruction, decode}};
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use super::global::*;
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use std::fs::File;
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/// doit disparaitre
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const MEM_SIZE : usize = 4096;
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pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
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impl RegisterNum for i64 {}
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impl RegisterNum for f32 {}
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pub struct Register<U: RegisterNum> {
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register: [U; 32]
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}
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impl<U: RegisterNum> Register<U> {
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pub fn get_reg(&self, position: usize) -> U {
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self.register[position]
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}
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}
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impl Register<i64> {
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pub fn init() -> Register<i64> {
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Register {
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register: [0i64; 32]
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}
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}
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pub fn set_reg(&mut self, position: usize, value: i64) {
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if position != 0 {
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self.register[position] = value;
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} else {
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// Panic ou rien ? (dans le doute pour le moment panic)
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unreachable!("You can't write to zero register")
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}
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}
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}
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impl Register<f32> {
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pub fn init() -> Register<f32> {
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Register {
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register: [0f32; 32]
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}
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}
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pub fn set_reg(&mut self, position: usize, value: f32) {
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self.register[position] = value;
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}
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}
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pub struct Machine {
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pub pc : u64,
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pub sp: usize,
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pub int_reg : Register<i64>,
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pub fp_reg : Register<f32>,
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pub main_memory : [u8 ; MEM_SIZE],
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pub shiftmask : [u64 ; 64]
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// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
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//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
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}
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impl Machine {
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pub fn _init_machine() -> Machine {
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let mut shiftmask : [u64 ; 64] = [0 ; 64];
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let mut value : u64 = 0xffffffff;
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value = (value << 32) + value;
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for item in &mut shiftmask {
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*item = value;
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value >>= 1;
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}
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Machine {
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pc : 0,
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sp: 0,
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int_reg : Register::<i64>::init(),
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fp_reg : Register::<f32>::init(),
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main_memory : [0 ; MEM_SIZE],
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shiftmask
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}
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}
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/// Read from main memory of the machine
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///
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/// `panic!` when size is not 1, 2, 4 or 8
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///
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/// ### Parameters
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///
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/// - **machine** which contains the main memory
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/// - **size** the number of bytes to read (1, 2, 4, 8)
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/// - **address** in the memory to read
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pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
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if ![1, 2, 4, 8].contains(&size) {
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panic!("ERROR read_memory : wrong size parameter {size}, must be (1, 2, 4 or 8)");
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}
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let mut ret: u64 = 0;
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for i in 0..size {
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ret <<= 8;
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ret += machine.main_memory[address + i as usize] as u64;
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}
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ret
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}
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/// Write to the main memory of the machine
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///
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/// `panic!` when size is not 1, 2, 4 or 8
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///
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/// ### Parameters
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///
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/// - **machine** contains the memory
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/// - **size** the number of bytes to write (1, 2, 4 or 8)
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/// - **address** the address to write to
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/// - **value** data to be written
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pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) {
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if ![1, 2, 4, 8].contains(&size) {
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panic!("ERROR write_memory: WRONG `size` PARAMETER ({size}), must be 1, 2, 4 or 8")
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}
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for i in 0..size as usize {
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let inv_i = size as usize - i - 1;
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machine.main_memory[address + i] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8;
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}
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}
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/// Write the contains of the main memory of the machine
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/// in a file called burritos_memory.txt
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///
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/// ### Parameters
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///
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/// - **machine** contains the memory
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pub fn extract_memory(machine: &mut Machine){
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let mut file = File::create("burritos_memory.txt").unwrap();
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file.write(&machine.main_memory);
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}
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/// Execute the instructions table of a machine putted in param
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions
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pub fn run(machine : Machine){
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let mut m = machine;
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for i in 0..MEM_SIZE{
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Machine::one_instruction(&mut m);
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}
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}
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/// execute the current instruction
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions and a pc to the actual instruction
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pub fn one_instruction(machine :&mut Machine) {
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let unsigned_reg1 : u64;
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let unsigned_reg2 : u64;
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let long_result : i128;
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/*__int128 longResult;
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int32_t local_data_a, local_data_b;
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int64_t localLongResult;
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uint32_t local_data_aUnsigned, local_data_bUnsigned;
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int32_t localResult;
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float localFloat;
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uint64_t value;*/
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if machine.main_memory.len() <= machine.pc as usize {
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println!("ERROR : number max of instructions rushed");
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return ;
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}
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let mut val: [u8; 8] = [0; 8];
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for i in 0..8 {
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val[i] = machine.main_memory[machine.pc as usize + i];
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}
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let val = u64::from_le_bytes(val);
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let inst : Instruction = decode(val);
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print!("executing instruction {}\n", val);
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print!("executing instruction {}\n", inst.opcode);
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match inst.opcode {
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RISCV_LUI => {
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machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
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},
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RISCV_AUIPC => {
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machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64);
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},
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RISCV_JAL => {
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machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
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machine.pc += inst.imm21_1_signed as u64 - 8;
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},
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RISCV_JALR => {
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let tmp = machine.pc;
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machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
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machine.int_reg.set_reg(inst.rd as usize, tmp as i64);
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},
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//******************************************************************************************
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// Treatment for: BRANCH INSTRUCTIONS
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RISCV_BR => {
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match inst.funct3 {
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RISCV_BR_BEQ => {
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if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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RISCV_BR_BNE => {
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if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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RISCV_BR_BLT => {
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if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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RISCV_BR_BGE => {
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if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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RISCV_BR_BLTU => {
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if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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RISCV_BR_BGEU => {
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if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc += inst.imm13_signed as u64 - 8;
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}
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},
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_ => {
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panic!("In BR switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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},
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//******************************************************************************************
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// Treatment for: LOAD INSTRUCTIONS
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RISCV_LD => {
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match inst.funct3 {
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RISCV_LD_LB | RISCV_LD_LBU => {
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let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LH | RISCV_LD_LHU => {
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let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LW | RISCV_LD_LWU => {
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let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LD => {
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let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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_ => {
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panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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},
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// store instructions
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RISCV_ST => {
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match inst.funct3 {
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RISCV_ST_STB => {
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Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
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},
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RISCV_ST_STH => {
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Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
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},
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RISCV_ST_STW => {
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Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
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},
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RISCV_ST_STD => {
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Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
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},
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_ => {
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panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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}
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//******************************************************************************************
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// Treatment for: OPI INSTRUCTIONS
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RISCV_OPI => {
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match inst.funct3 {
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RISCV_OPI_ADDI => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64);
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},
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RISCV_OPI_SLTI => {
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machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } );
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},
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RISCV_OPI_XORI => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64);
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},
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RISCV_OPI_ORI => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64);
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},
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RISCV_OPI_ANDI => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64);
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},
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RISCV_OPI_SLLI => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt);
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},
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RISCV_OPI_SRI => {
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if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
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machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64);
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} else { // SRAI
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt);
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}
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}
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_ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); }
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}
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},
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RISCV_OP => {
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if inst.funct7 == 1 {
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match inst.funct3 {
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RISCV_OP_M_MUL => {
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long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
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machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64);
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},
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RISCV_OP_M_MULH => {
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long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
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machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
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},
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RISCV_OP_M_MULHSU => {
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unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
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long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128;
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machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
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},
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// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
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/*
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* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
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* WHAT DA HECK
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*/
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RISCV_OP_M_MULHU => {
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unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
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unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
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long_result = (unsigned_reg1 * unsigned_reg2) as i128;
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machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
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},
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RISCV_OP_M_DIV => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize));
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}
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_ => {
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panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
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}
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}
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} else {
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match inst.funct3 {
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RISCV_OP_ADD => {
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if inst.funct7 == RISCV_OP_ADD_ADD {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize));
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} else {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize));
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}
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},
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RISCV_OP_SLL => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f));
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},
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RISCV_OP_SLT => {
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if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.int_reg.set_reg(inst.rd as usize, 1);
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} else {
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machine.int_reg.set_reg(inst.rd as usize, 0);
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}
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},
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RISCV_OP_SLTU => {
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unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
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unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
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if unsigned_reg1 < unsigned_reg2 {
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machine.int_reg.set_reg(inst.rd as usize, 1);
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} else {
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machine.int_reg.set_reg(inst.rd as usize, 0);
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}
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},
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RISCV_OP_XOR => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize));
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},
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RISCV_OP_SR => {
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// RISCV_OP_SR_SRL inaccessible
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize));
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},
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RISCV_OP_OR => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize));
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},
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RISCV_OP_AND => {
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize));
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},
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_ => {
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panic!("RISCV_OP undefined case\n");
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}
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}//LA
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}
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},
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//******************************************************************************************
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// Treatment for OPIW INSTRUCTIONS
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RISCV_OPIW => {
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let local_data = machine.int_reg.get_reg(inst.rs1 as usize);
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match inst.funct3 {
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RISCV_OPIW_ADDIW => {
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let result = local_data + inst.imm12_I_signed as i64;
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machine.int_reg.set_reg(inst.rd as usize, result);
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},
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RISCV_OPIW_SLLIW => {
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let result = local_data << inst.shamt;
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machine.int_reg.set_reg(inst.rd as usize, result);
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},
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RISCV_OPIW_SRW => {
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|
let result;
|
|
if inst.funct7 == RISCV_OPIW_SRW_SRLIW {
|
|
result = (local_data >> inst.shamt) & machine.shiftmask[32 + inst.shamt as usize] as i64;
|
|
} else { // SRAIW
|
|
result = local_data >> inst.shamt;
|
|
}
|
|
machine.int_reg.set_reg(inst.rd as usize, result);
|
|
},
|
|
_ => {
|
|
panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value);
|
|
}
|
|
}
|
|
},
|
|
//******************************************************************************************
|
|
// Treatment for: OPW INSTRUCTIONS
|
|
RISCV_OPW => {
|
|
if inst.funct7 == 1 { // rv64m
|
|
let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
|
|
// Match case for multiplication operations (in standard extension RV32M)
|
|
match inst.funct3 {
|
|
RISCV_OPW_M_MULW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b);
|
|
},
|
|
RISCV_OPW_M_DIVW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b);
|
|
},
|
|
RISCV_OPW_M_DIVUW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned);
|
|
},
|
|
RISCV_OPW_M_REMW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b);
|
|
},
|
|
RISCV_OPW_M_REMUW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned);
|
|
},
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
} else { // others rv64 OPW operations
|
|
let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
|
|
// Match case for base OP operation
|
|
match inst.funct3 {
|
|
RISCV_OPW_ADDSUBW => {
|
|
if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab);
|
|
} else { // SUBW
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab);
|
|
}
|
|
},
|
|
RISCV_OPW_SLLW => {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f));
|
|
},
|
|
RISCV_OPW_SRW => {
|
|
if inst.funct7 == RISCV_OPW_SRW_SRLW {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64);
|
|
} else { // SRAW
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f));
|
|
}
|
|
},
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
}
|
|
},
|
|
//******************************************************************************************
|
|
// Treatment for: Simple floating point extension
|
|
RISCV_FP => {
|
|
match inst.funct7 {
|
|
RISCV_FP_ADD => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize));
|
|
},
|
|
RISCV_FP_SUB => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize));
|
|
},
|
|
RISCV_FP_MUL => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize));
|
|
},
|
|
RISCV_FP_DIV => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize));
|
|
},
|
|
RISCV_FP_SQRT => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt());
|
|
},
|
|
RISCV_FP_FSGN => {
|
|
let local_float = machine.fp_reg.get_reg(inst.rs1 as usize);
|
|
match inst.funct3 {
|
|
RISCV_FP_FSGN_J => {
|
|
if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float);
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float);
|
|
}
|
|
}
|
|
RISCV_FP_FSGN_JN => {
|
|
if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float);
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float);
|
|
}
|
|
}
|
|
RISCV_FP_FSGN_JX => {
|
|
if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float);
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float);
|
|
}
|
|
}
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
},
|
|
RISCV_FP_MINMAX => {
|
|
let r1 = machine.fp_reg.get_reg(inst.rs1 as usize);
|
|
let r2 = machine.fp_reg.get_reg(inst.rs2 as usize);
|
|
match inst.funct3 {
|
|
RISCV_FP_MINMAX_MIN => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2});
|
|
},
|
|
RISCV_FP_MINMAX_MAX => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2});
|
|
},
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
},
|
|
RISCV_FP_FCVTW => {
|
|
if inst.rs2 == RISCV_FP_FCVTW_W {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
|
|
} else {
|
|
machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64);
|
|
}
|
|
},
|
|
RISCV_FP_FCVTS => {
|
|
if inst.rs2 == RISCV_FP_FCVTS_W {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32);
|
|
}
|
|
},
|
|
RISCV_FP_FMVW => {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
|
|
},
|
|
RISCV_FP_FMVXFCLASS => {
|
|
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
|
|
} else {
|
|
panic!("Fclass instruction is not handled in riscv simulator");
|
|
}
|
|
},
|
|
RISCV_FP_FCMP => {
|
|
match inst.funct3 {
|
|
RISCV_FP_FCMP_FEQ => {
|
|
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
|
|
},
|
|
RISCV_FP_FCMP_FLT => {
|
|
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
|
|
},
|
|
RISCV_FP_FCMP_FLE => {
|
|
machine.int_reg.set_reg(inst.rd as usize, if machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize) {1} else {0});
|
|
},
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
},
|
|
_ => {
|
|
panic!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
}
|
|
_ => { panic!("{} opcode non géré", inst.opcode)},
|
|
}
|
|
|
|
machine.pc += 8;
|
|
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod test {
|
|
use crate::simulator::machine::Machine;
|
|
|
|
#[test]
|
|
fn test_read_memory() {
|
|
let mut m = Machine::_init_machine();
|
|
m.main_memory[4] = 43;
|
|
m.main_memory[5] = 150;
|
|
assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4));
|
|
}
|
|
|
|
#[test]
|
|
fn test_write_memory() {
|
|
let mut m = Machine::_init_machine();
|
|
Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
|
|
assert_eq!(43, m.main_memory[6]);
|
|
assert_eq!(150, m.main_memory[7]);
|
|
}
|
|
}
|