382 lines
13 KiB
Rust
382 lines
13 KiB
Rust
use super::{decode::{Instruction, decode}, print::*};
|
|
|
|
/// doit disparaitre
|
|
const MEM_SIZE : usize= 4096;
|
|
|
|
pub struct Machine {
|
|
pub pc : u64,
|
|
pub int_reg : [i64 ; 32],
|
|
pub instructions : [u64 ; 100],
|
|
pub main_memory : [u8 ; MEM_SIZE],
|
|
pub shiftmask : [u64 ; 64]
|
|
// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
|
|
//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
|
|
}
|
|
|
|
|
|
impl Machine {
|
|
|
|
pub fn _init_machine() -> Machine {
|
|
let mut shiftmask : [u64 ; 64] = [0 ; 64];
|
|
let mut value : u64 = 0xffffffff;
|
|
|
|
value = (value << 32) + value;
|
|
for item in &mut shiftmask {
|
|
*item = value;
|
|
value >>= 1;
|
|
}
|
|
|
|
Machine {
|
|
pc : 0,
|
|
instructions : [0 ; 100],
|
|
int_reg : [0 ; 32],
|
|
main_memory : [0 ; MEM_SIZE],
|
|
shiftmask
|
|
}
|
|
}
|
|
|
|
/// Read from main memory of the machine
|
|
///
|
|
/// ### Parameters
|
|
///
|
|
/// - **machine** which contains the main memory
|
|
/// - **size** the number of bytes to read (1, 2, 4, 8)
|
|
/// - **address** in the memory to read
|
|
pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
|
|
if size != 1 && size != 2 && size != 4 && size != 8 {
|
|
panic!("ERROR read_memory : wrong size parameter {}, must be (1, 2, 4 or 8)", size);
|
|
}
|
|
|
|
let mut ret : u64 = machine.main_memory[address] as u64;
|
|
if size == 2 || size == 4 || size == 8 {
|
|
ret <<= 8;
|
|
ret += machine.main_memory[address + 1] as u64;
|
|
}
|
|
if size == 4 || size == 8 {
|
|
ret <<= 8;
|
|
ret += machine.main_memory[address + 2] as u64;
|
|
}
|
|
if size == 8 {
|
|
ret <<= 8;
|
|
ret += machine.main_memory[address + 3] as u64;
|
|
}
|
|
ret
|
|
}
|
|
|
|
/// Execute the instructions table of a machine putted in param
|
|
///
|
|
/// ### Parameters
|
|
///
|
|
/// - **machine** which contains a table of instructions
|
|
pub fn run(machine : Machine){
|
|
let mut m = machine;
|
|
loop{
|
|
Machine::one_instruction(&mut m);
|
|
}
|
|
}
|
|
|
|
/// execute the current instruction
|
|
///
|
|
/// ### Parameters
|
|
///
|
|
/// - **machine** which contains a table of instructions and a pc to the actual instruction
|
|
pub fn one_instruction(machine :&mut Machine) {
|
|
|
|
let unsigned_reg1 : u64;
|
|
let unsigned_reg2 : u64;
|
|
let long_result : i128;
|
|
|
|
/*__int128 longResult;
|
|
int32_t local_data_a, local_data_b;
|
|
int64_t localLongResult;
|
|
uint32_t local_data_aUnsigned, local_data_bUnsigned;
|
|
int32_t localResult;
|
|
float localFloat;
|
|
uint64_t value;*/
|
|
|
|
if machine.instructions.len() <= machine.pc as usize {
|
|
println!("ERROR : number max of instructions rushed");
|
|
return ;
|
|
}
|
|
|
|
let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
|
|
|
|
|
|
match inst.opcode {
|
|
RISCV_LUI => {
|
|
machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64;
|
|
},
|
|
RISCV_AUIPC => {
|
|
machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64;
|
|
},
|
|
RISCV_JAL => {
|
|
machine.int_reg[inst.rd as usize] = machine.pc as i64;
|
|
machine.pc += inst.imm21_1_signed as u64 - 4;
|
|
},
|
|
RISCV_JALR => {
|
|
let tmp = machine.pc;
|
|
machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
|
|
machine.int_reg[inst.rd as usize] = tmp as i64;
|
|
},
|
|
|
|
//******************************************************************************************
|
|
// Treatment for: BRANCH INSTRUCTIONS
|
|
RISCV_BR => {
|
|
match inst.funct3 {
|
|
RISCV_BR_BEQ => {
|
|
if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
RISCV_BR_BNE => {
|
|
if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
RISCV_BR_BLT => {
|
|
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
RISCV_BR_BGE => {
|
|
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
RISCV_BR_BLTU => {
|
|
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
RISCV_BR_BGEU => {
|
|
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] {
|
|
machine.pc += inst.imm13_signed as u64 - 4;
|
|
}
|
|
},
|
|
_ => {
|
|
println!("In BR switch case, this should never happen... Instr was {}", inst.value);
|
|
}
|
|
}
|
|
},
|
|
|
|
//******************************************************************************************
|
|
// Treatment for: LOAD INSTRUCTIONS
|
|
RISCV_LD => {
|
|
match inst.funct3 {
|
|
RISCV_LD_LB => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
RISCV_LD_LH => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
RISCV_LD_LW => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
RISCV_LD_LD => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
|
|
// same thing three opration ?
|
|
RISCV_LD_LBU => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
RISCV_LD_LHU => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
RISCV_LD_LWU => {
|
|
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
|
|
},
|
|
_ => {
|
|
println!("In LD switch case, this should never happen... Instr was {}", inst.value);
|
|
}
|
|
}
|
|
},
|
|
|
|
//TODO store instructions
|
|
|
|
//******************************************************************************************
|
|
// Treatment for: OPI INSTRUCTIONS
|
|
RISCV_OPI => {
|
|
match inst.funct3 {
|
|
RISCV_OPI_ADDI => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64;
|
|
},
|
|
RISCV_OPI_SLTI => {
|
|
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64;
|
|
},
|
|
RISCV_OPI_XORI => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64;
|
|
},
|
|
RISCV_OPI_ORI => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64;
|
|
},
|
|
RISCV_OPI_ANDI => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64;
|
|
},
|
|
RISCV_OPI_SLLI => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt;
|
|
},
|
|
RISCV_OPI_SRI => {
|
|
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
|
|
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64;
|
|
} else { // SRAI
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;
|
|
}
|
|
}
|
|
_ => { println!("{} inconnu", inst.funct3); }
|
|
}
|
|
},
|
|
|
|
RISCV_OP => {
|
|
if inst.funct7 == 1{
|
|
match inst.funct3 {
|
|
RISCV_OP_M_MUL => {
|
|
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
|
|
machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64;
|
|
},
|
|
RISCV_OP_M_MULH => {
|
|
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128;
|
|
|
|
},
|
|
RISCV_OP_M_MULHSU => {
|
|
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
|
|
long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128;
|
|
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
|
|
},
|
|
// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
|
|
/*
|
|
* VOIR SI LES CAST machine.int_reg[....] = i128*u64 as u32 FAUSSE RESULTAT (suit pas la logique du code c++)
|
|
* WHAT DA HECK
|
|
*/
|
|
RISCV_OP_M_MULHU => {
|
|
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
|
|
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
|
|
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
|
|
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64;
|
|
},
|
|
RISCV_OP_M_DIV => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize];
|
|
}
|
|
_ => {
|
|
println!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
|
|
}
|
|
}
|
|
} else {
|
|
match inst.funct3 {
|
|
RISCV_OP_ADD => {
|
|
if inst.funct7 == RISCV_OP_ADD_ADD {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];
|
|
} else {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
|
|
}
|
|
},
|
|
RISCV_OP_SLL => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
|
|
},
|
|
RISCV_OP_SLT => {
|
|
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] {
|
|
machine.int_reg[inst.rd as usize] = 1;
|
|
} else {
|
|
machine.int_reg[inst.rd as usize] = 0;
|
|
}
|
|
},
|
|
RISCV_OP_SLTU => {
|
|
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64;
|
|
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64;
|
|
if unsigned_reg1 < unsigned_reg2 {
|
|
machine.int_reg[inst.rd as usize] = 1;
|
|
} else {
|
|
machine.int_reg[inst.rd as usize] = 0;
|
|
}
|
|
},
|
|
RISCV_OP_XOR => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
|
|
},
|
|
RISCV_OP_SR => {
|
|
// RISCV_OP_SR_SRL inaccessible
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
|
|
},
|
|
RISCV_OP_OR => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
|
|
},
|
|
RISCV_OP_AND => {
|
|
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
|
|
},
|
|
_ => {
|
|
println!("RISCV_OP undefined case\n");
|
|
}
|
|
}//LA
|
|
}
|
|
},
|
|
//******************************************************************************************
|
|
// Treatment for: OPW INSTRUCTIONS
|
|
RISCV_OPW => {
|
|
if inst.funct7 == 1 {
|
|
let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
|
|
let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
|
|
let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
|
|
let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
|
|
|
|
// Match case for multiplication operations (in standard extension RV32M)
|
|
match inst.funct3 {
|
|
RISCV_OPW_M_MULW => {
|
|
machine.int_reg[inst.rd as usize] = local_data_a * local_data_b;
|
|
},
|
|
RISCV_OPW_M_DIVW => {
|
|
machine.int_reg[inst.rd as usize] = local_data_a / local_data_b;
|
|
},
|
|
RISCV_OPW_M_DIVUW => {
|
|
machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned;
|
|
},
|
|
RISCV_OPW_M_REMW => {
|
|
machine.int_reg[inst.rd as usize] = local_data_a % local_data_b;
|
|
},
|
|
RISCV_OPW_M_REMUW => {
|
|
machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned;
|
|
},
|
|
_ => {
|
|
println!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
} else {
|
|
let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff;
|
|
let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff;
|
|
|
|
// Match case for base OP operation
|
|
match inst.funct3 {
|
|
RISCV_OPW_ADDSUBW => {
|
|
if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
|
|
machine.int_reg[inst.rd as usize] = local_dataa + local_datab;
|
|
} else { // SUBW
|
|
machine.int_reg[inst.rd as usize] = local_dataa - local_datab;
|
|
}
|
|
},
|
|
RISCV_OPW_SLLW => {
|
|
machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f);
|
|
},
|
|
RISCV_OPW_SRW => {
|
|
if inst.funct7 == RISCV_OPW_SRW_SRLW {
|
|
machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64;
|
|
} else { // SRAW
|
|
machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f);
|
|
}
|
|
},
|
|
_ => {
|
|
println!("this instruction ({}) doesn't exists", inst.value);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
_ => { println!("{} opcode non géré", inst.opcode)},
|
|
}
|
|
|
|
machine.pc += 4;
|
|
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod test {
|
|
|
|
}
|