Quentin Legot 453de4b704 Fix is_riscv_isa		2023-03-31 15:34:04 +02:00
..
decode.rs	Add a lot of comments, fix SRLI instruction in print,	2023-01-18 22:15:06 +01:00
error.rs	♻️ Error cleanup	2023-03-28 19:37:31 +02:00
interrupt.rs	use of system in parameters in synch	2023-03-15 11:09:34 +01:00
loader.rs	Fix is_riscv_isa	2023-03-31 15:34:04 +02:00
machine.rs	Loader seem to work, be seem we have a problem with jalr	2023-03-28 21:26:58 +02:00
mem_cmp.rs	oups sorry les boys	2023-03-15 15:48:58 +01:00
mmu.rs	Renamed exceptions to follow CamlCase convention	2023-03-23 20:54:05 +01:00
mod.rs	📝 Documentation updates	2023-03-24 19:02:50 +01:00
print.rs	Add a bin loader	2023-03-27 18:10:11 +02:00
register.rs	📝 Documentation updates	2023-03-24 19:02:50 +01:00
translationtable.rs	impl translation table + debut impl mmu	2023-03-13 22:52:27 +01:00