758 lines
29 KiB
Rust
758 lines
29 KiB
Rust
use std::{ops::{Add, Sub}, io::Write};
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use crate::simulator::{print, error::MachineError};
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use super::{decode::{Instruction, decode}, interrupt::Interrupt};
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use super::global::*;
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use std::fs::File;
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/*
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* Decommenter la variant si il est utilisé quelque part
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*/
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pub enum ExceptionType {
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//Everything ok!
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NoException,
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//SYSCALL_EXCEPTION,//A program executed a system call.
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PagefaultException,//Page fault exception
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ReadOnlyException,//Write attempted to a page marked "read-only" */
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BusErrorException,
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/* translation resulted
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in an invalid physical
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address (mis-aligned or
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out-of-bounds) */
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AddressErrorException, /* Reference that was
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not mapped in the address
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space */
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//OVERFLOW_EXCEPTION, //Integer overflow in add or sub.
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//ILLEGALINSTR_EXCEPTION, //Unimplemented or reserved instr.
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//NUM_EXCEPTION_TYPES
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}
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pub const STACK_REG: usize = 2;
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pub const NUM_INT_REGS: usize = 32;
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pub const NUM_FP_REGS: usize = 32;
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/// max number of physical pages
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pub const NUM_PHY_PAGE : u64 = 400;
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/// Must be 2^x
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pub const PAGE_SIZE : u64 = 128;
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/// Must be a multiple of PAGE_SIZE
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pub const MEM_SIZE : usize = (PAGE_SIZE*NUM_PHY_PAGE*100) as usize;
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pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
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impl RegisterNum for i64 {}
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impl RegisterNum for f32 {}
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#[derive(PartialEq)]
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pub struct Register<U: RegisterNum> {
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register: [U; 32]
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}
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impl<U: RegisterNum> Register<U> {
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pub fn get_reg(&self, position: usize) -> U {
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self.register[position]
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}
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}
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impl Register<i64> {
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pub fn init() -> Register<i64> {
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Register {
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register: [0i64; 32]
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}
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}
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pub fn set_reg(&mut self, position: usize, value: i64) {
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if position != 0 {
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self.register[position] = value;
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} else {
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// Panic ou rien ? (dans le doute pour le moment panic)
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// unreachable!("You can't write to zero register")
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}
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}
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}
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impl Register<f32> {
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pub fn init() -> Register<f32> {
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Register {
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register: [0f32; 32]
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}
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}
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pub fn set_reg(&mut self, position: usize, value: f32) {
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self.register[position] = value;
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}
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}
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#[derive(PartialEq)]
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pub struct Machine {
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pub pc : u64,
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pub sp: usize,
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pub int_reg : Register<i64>,
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pub fp_reg : Register<f32>,
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pub main_memory : Vec<u8>,
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pub shiftmask : [u64 ; 64],
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pub registers_trace : String, // for tests
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pub interrupt: Interrupt
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// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
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//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
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}
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impl Machine {
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pub fn init_machine() -> Machine {
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let mut shiftmask : [u64 ; 64] = [0 ; 64];
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let mut value : u64 = 0xffffffff;
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value = (value << 32) + value;
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for item in &mut shiftmask {
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*item = value;
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value >>= 1;
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}
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let mut ret = Machine {
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pc : 0,
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sp: 0,
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int_reg : Register::<i64>::init(),
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fp_reg : Register::<f32>::init(),
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main_memory : vec![0_u8; MEM_SIZE],
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shiftmask,
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interrupt: Interrupt::new(),
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registers_trace : String::from("")
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};
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ret.int_reg.set_reg(10, -1);
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ret
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}
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/// Read from main memory of the machine
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///
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/// `panic!` when size is not 1, 2, 4 or 8
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///
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/// ### Parameters
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///
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/// - **machine** which contains the main memory
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/// - **size** the number of bytes to read (1, 2, 4, 8)
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/// - **address** in the memory to read
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pub fn read_memory(machine : &mut Machine, size : i32, address : usize) -> u64 {
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if ![1, 2, 4, 8].contains(&size) {
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panic!("ERROR read_memory : wrong size parameter {size}, must be (1, 2, 4 or 8)");
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}
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let mut ret: u64 = 0;
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for i in 0..size {
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ret <<= 8;
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ret += machine.main_memory[address + i as usize] as u64;
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}
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ret
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}
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/// Write to the main memory of the machine
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///
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/// `panic!` when size is not 1, 2, 4 or 8
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///
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/// ### Parameters
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///
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/// - **machine** contains the memory
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/// - **size** the number of bytes to write (1, 2, 4 or 8)
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/// - **address** the address to write to
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/// - **value** data to be written
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pub fn write_memory(machine: &mut Machine, size: i32, address: usize, value: u64) {
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if ![1, 2, 4, 8].contains(&size) {
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panic!("ERROR write_memory: WRONG `size` PARAMETER ({size}), must be 1, 2, 4 or 8")
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}
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for i in 0..size as usize {
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let inv_i = size as usize - i - 1;
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machine.main_memory[address + i] = ((value & 0xff << (8 * inv_i)) >> (inv_i * 8)) as u8;
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}
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}
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/// Write the contains of the main memory of the machine
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/// in a file called burritos_memory.txt
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///
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/// ### Parameters
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///
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/// - **machine** contains the memory
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pub fn _extract_memory(machine: &mut Machine){
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let file_path = "burritos_memory.txt";
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let write_to_file = |path| -> std::io::Result<File> {
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let mut file = File::create(path)?;
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file.write_all(&machine.main_memory)?;
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Ok(file)
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};
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match write_to_file(file_path) {
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Err(e) => eprintln!("Failed to write memory to file: {}", e),
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Ok(_) => println!("Memory extracted to {}", file_path)
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};
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}
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pub fn print_machine_status(machine: &mut Machine) {
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println!("######### Machine status #########");
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for i in (0..32).step_by(3) {
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print!(">{0: <4} : {1:<16x} ", print::REG_X[i], machine.int_reg.get_reg(i));
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print!(">{0: <4} : {1:<16x} ", print::REG_X[i+1], machine.int_reg.get_reg(i+1));
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if i+2 < 32 {
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print!(">{0: <4} : {1:<16x} ", print::REG_X[i+2], machine.int_reg.get_reg(i+2));
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}
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println!();
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}
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println!("________________SP________________");
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let sp_index = machine.int_reg.get_reg(2);
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for i in 0..5 {
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println!("SP+{:<2} : {:16x}", i*8, Self::read_memory(machine, 8, (sp_index + i*8) as usize));
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}
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println!("##################################");
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}
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pub fn string_registers(machine: &mut Machine) -> String {
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let mut s = String::from("");
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for i in 0..32 {
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s.push_str(format!("{} ", machine.int_reg.get_reg(i)).as_str());
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}
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s
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}
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/// Execute the instructions table of a machine putted in param
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions
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pub fn run(machine : &mut Machine){
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while let Ok(()) = Machine::one_instruction(machine) {}
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println!("trace : \n{}", machine.registers_trace);
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}
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/// Execute the current instruction
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///
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/// ### Parameters
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///
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/// - **machine** which contains a table of instructions and a pc to the actual instruction
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pub fn one_instruction(machine :&mut Machine) -> Result<(), MachineError> {
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if machine.main_memory.len() <= machine.pc as usize {
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panic!("ERROR : number max of instructions rushed");
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}
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let mut val: [u8; 4] = [0; 4];
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for i in 0..4 {
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val[i] = machine.main_memory[machine.pc as usize + i];
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}
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let val = u32::from_be_bytes(val) as u64;
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let inst : Instruction = decode(val);
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Self::print_machine_status(machine);
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println!("executing instruction : {:016x} at pc {:x}", val, machine.pc);
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println!("{}", print::print(decode(val), machine.pc as i32));
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let trace = Self::string_registers(machine);
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machine.registers_trace.push_str(format!("{}\n", trace).as_str());
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machine.pc += 4;
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match inst.opcode {
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RISCV_LUI => {
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machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
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Ok(())
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},
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RISCV_AUIPC => {
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machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
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Ok(())
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},
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RISCV_JAL => {
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machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
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machine.pc = (machine.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64;
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Ok(())
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},
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RISCV_JALR => {
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let tmp = machine.pc;
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machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe;
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machine.int_reg.set_reg(inst.rd as usize, tmp as i64);
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Ok(())
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},
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// Treatment for: BRANCH INSTRUCTIONS
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RISCV_BR => {
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Self::branch_instruction(machine, inst)
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},
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// Treatment for: LOAD INSTRUCTIONS
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RISCV_LD => {
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Self::load_instruction(machine, inst)
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},
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// store instructions
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RISCV_ST => {
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Self::store_instruction(machine, inst)
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},
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// Treatment for: OPI INSTRUCTIONS
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RISCV_OPI => {
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Self::opi_instruction(machine, inst)
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},
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RISCV_OP => {
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Self::op_instruction(machine, inst)
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},
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// Treatment for OPIW INSTRUCTIONS
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RISCV_OPIW => {
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Self::opiw_instruction(machine, inst)
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},
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// Treatment for: OPW INSTRUCTIONS
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RISCV_OPW => Self::opw_instruction(machine, inst),
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// Treatment for: Simple floating point extension
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RISCV_FP => Self::fp_instruction(machine, inst),
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// Treatment for: System instructions
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RISCV_SYSTEM => {
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// temporary return value to stop the loop of run
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// before we can use system call
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Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, machine.pc).as_str()))
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},
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_ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, machine.pc).as_str()))
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}
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}
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/// Treatement for Branch instructions
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fn branch_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
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match inst.funct3 {
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RISCV_BR_BEQ => {
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if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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RISCV_BR_BNE => {
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if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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RISCV_BR_BLT => {
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if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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RISCV_BR_BGE => {
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if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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RISCV_BR_BLTU => {
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if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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RISCV_BR_BGEU => {
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if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
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machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64;
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}
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},
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_ => {
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panic!("In BR switch case, this should never happen... Instr was {}", inst.value);
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}
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}
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Ok(())
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}
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/// Executes RISC-V Load Instructions on the machine
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fn load_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
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match inst.funct3 {
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RISCV_LD_LB | RISCV_LD_LBU => {
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let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LH | RISCV_LD_LHU => {
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let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LW | RISCV_LD_LWU => {
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let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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RISCV_LD_LD => {
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let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
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machine.int_reg.set_reg(inst.rd as usize, tmp);
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},
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_ => panic!("In LD switch case, this should never happen... Instr was {}", inst.value)
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}
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Ok(())
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}
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/// Executes RISC-V Store Instructions on the machine
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fn store_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
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match inst.funct3 {
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RISCV_ST_STB => Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64),
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RISCV_ST_STH => Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64),
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RISCV_ST_STW => Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64),
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RISCV_ST_STD => Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64),
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_ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value)
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}
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Ok(())
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}
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/// Executes RISC-V Integer Register-Immediate Instructions on the machine
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fn opi_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
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match inst.funct3 {
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RISCV_OPI_ADDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64),
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RISCV_OPI_SLTI => machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64) as i64),
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RISCV_OPI_XORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64),
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RISCV_OPI_ORI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64),
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RISCV_OPI_ANDI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64),
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RISCV_OPI_SLLI => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt),
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RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
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machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64);
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} else { // SRAI
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machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt);
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},
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_ => panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value)
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}
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Ok(())
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}
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/// Executes simple RISC-V mathematical operations on the machine
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fn op_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
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let long_result: i128;
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let unsigned_reg1: u64;
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let unsigned_reg2: u64;
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if inst.funct7 == 1 {
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match inst.funct3 {
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RISCV_OP_M_MUL => {
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long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
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machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64)
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},
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RISCV_OP_M_MULH => {
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long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
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machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64)
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},
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RISCV_OP_M_MULHSU => {
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unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
|
|
long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128;
|
|
machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64)
|
|
},
|
|
RISCV_OP_M_MULHU => {
|
|
unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
|
|
unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
|
|
long_result = (unsigned_reg1 * unsigned_reg2) as i128;
|
|
machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
|
|
},
|
|
RISCV_OP_M_DIV => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize)),
|
|
_ => panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n")
|
|
}
|
|
} else {
|
|
match inst.funct3 {
|
|
RISCV_OP_ADD => if inst.funct7 == RISCV_OP_ADD_ADD {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize))
|
|
} else {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize))
|
|
},
|
|
RISCV_OP_SLL => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f)),
|
|
RISCV_OP_SLT => if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
|
|
machine.int_reg.set_reg(inst.rd as usize, 1)
|
|
} else {
|
|
machine.int_reg.set_reg(inst.rd as usize, 0)
|
|
},
|
|
RISCV_OP_SLTU => {
|
|
unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
|
|
unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
|
|
if unsigned_reg1 < unsigned_reg2 {
|
|
machine.int_reg.set_reg(inst.rd as usize, 1)
|
|
} else {
|
|
machine.int_reg.set_reg(inst.rd as usize, 0)
|
|
}
|
|
},
|
|
RISCV_OP_XOR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_OP_SR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize)), // RISCV_OP_SR_SRL inaccessible
|
|
RISCV_OP_OR => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_OP_AND => machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize)),
|
|
_ => panic!("RISCV_OP undefined case\n")
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
/// Exectutes simple RISC-V *iw instructions on the machine
|
|
fn opiw_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
|
|
let local_data = machine.int_reg.get_reg(inst.rs1 as usize);
|
|
match inst.funct3 {
|
|
RISCV_OPIW_ADDIW => {
|
|
let result = local_data + inst.imm12_I_signed as i64;
|
|
machine.int_reg.set_reg(inst.rd as usize, result)
|
|
},
|
|
RISCV_OPIW_SLLIW => {
|
|
let result = local_data << inst.shamt;
|
|
machine.int_reg.set_reg(inst.rd as usize, result)
|
|
},
|
|
RISCV_OPIW_SRW => {
|
|
let result = if inst.funct7 == RISCV_OPIW_SRW_SRLIW {
|
|
(local_data >> inst.shamt) & machine.shiftmask[32 + inst.shamt as usize] as i64
|
|
} else { // SRAIW
|
|
local_data >> inst.shamt
|
|
};
|
|
machine.int_reg.set_reg(inst.rd as usize, result)
|
|
},
|
|
_ => panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value),
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
/// Executes simple RISC-V *w instructions on the machine
|
|
fn opw_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
|
|
if inst.funct7 == 1 { // rv64m
|
|
let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
|
|
// Match case for multiplication operations (in standard extension RV32M)
|
|
match inst.funct3 {
|
|
RISCV_OPW_M_MULW => machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b),
|
|
RISCV_OPW_M_DIVW => machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b),
|
|
RISCV_OPW_M_DIVUW => machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned),
|
|
RISCV_OPW_M_REMW => machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b),
|
|
RISCV_OPW_M_REMUW => machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned),
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
} else { // others rv64 OPW operations
|
|
let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
|
|
let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
|
|
// Match case for base OP operation
|
|
match inst.funct3 {
|
|
RISCV_OPW_ADDSUBW => if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab);
|
|
} else { // SUBW
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab);
|
|
},
|
|
RISCV_OPW_SLLW => machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f)),
|
|
RISCV_OPW_SRW => if inst.funct7 == RISCV_OPW_SRW_SRLW {
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64)
|
|
} else { // SRAW
|
|
machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f))
|
|
},
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
/// Executes simple RISC-V floating point instructions on the machine
|
|
fn fp_instruction(machine: &mut Machine, inst: Instruction) -> Result<(), MachineError> {
|
|
match inst.funct7 {
|
|
RISCV_FP_ADD => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_FP_SUB => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_FP_MUL => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_FP_DIV => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize)),
|
|
RISCV_FP_SQRT => machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt()),
|
|
RISCV_FP_FSGN => {
|
|
let local_float = machine.fp_reg.get_reg(inst.rs1 as usize);
|
|
match inst.funct3 {
|
|
RISCV_FP_FSGN_J => if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float)
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float)
|
|
},
|
|
RISCV_FP_FSGN_JN => if machine.fp_reg.get_reg(inst.rs2 as usize) < 0f32 {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float)
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float)
|
|
},
|
|
RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
|
|
machine.fp_reg.set_reg(inst.rd as usize, -local_float)
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, local_float)
|
|
},
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
},
|
|
RISCV_FP_MINMAX => {
|
|
let r1 = machine.fp_reg.get_reg(inst.rs1 as usize);
|
|
let r2 = machine.fp_reg.get_reg(inst.rs2 as usize);
|
|
match inst.funct3 {
|
|
RISCV_FP_MINMAX_MIN => machine.fp_reg.set_reg(inst.rd as usize, if r1 < r2 {r1} else {r2}),
|
|
RISCV_FP_MINMAX_MAX => machine.fp_reg.set_reg(inst.rd as usize, if r1 > r2 {r1} else {r2}),
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
},
|
|
RISCV_FP_FCVTW => {
|
|
if inst.rs2 == RISCV_FP_FCVTW_W {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64)
|
|
} else {
|
|
machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) as u64) as i64)
|
|
}
|
|
},
|
|
RISCV_FP_FCVTS => {
|
|
if inst.rs2 == RISCV_FP_FCVTS_W {
|
|
machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32);
|
|
} else {
|
|
machine.fp_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) as u32) as f32);
|
|
}
|
|
},
|
|
RISCV_FP_FMVW => machine.fp_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) as f32),
|
|
RISCV_FP_FMVXFCLASS => {
|
|
if inst.funct3 == RISCV_FP_FMVXFCLASS_FMVX {
|
|
machine.int_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) as i64);
|
|
} else {
|
|
panic!("Fclass instruction is not handled in riscv simulator");
|
|
}
|
|
},
|
|
RISCV_FP_FCMP => {
|
|
match inst.funct3 {
|
|
RISCV_FP_FCMP_FEQ => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) == machine.fp_reg.get_reg(inst.rs2 as usize)) as i64),
|
|
RISCV_FP_FCMP_FLT => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) < machine.fp_reg.get_reg(inst.rs2 as usize)) as i64),
|
|
RISCV_FP_FCMP_FLE => machine.int_reg.set_reg(inst.rd as usize, (machine.fp_reg.get_reg(inst.rs1 as usize) <= machine.fp_reg.get_reg(inst.rs2 as usize)) as i64),
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
},
|
|
_ => panic!("this instruction ({}) doesn't exists", inst.value)
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
/// print memory FOR DEBUG
|
|
///
|
|
/// "@"adresse [16 bytes]
|
|
pub fn _print_memory(machine : &mut Machine, from: usize, to: usize) {
|
|
for i in from..to {
|
|
if i%16 == 0 {
|
|
print!("\n@{:04x} ", i);
|
|
}
|
|
print!("{:02x}", machine.main_memory[i]);
|
|
}
|
|
println!();
|
|
}
|
|
|
|
pub fn read_int_register(&self, index: usize) -> i64 {
|
|
self.int_reg.get_reg(index)
|
|
}
|
|
|
|
pub fn read_fp_register(&self, index: usize) -> f32 {
|
|
self.fp_reg.get_reg(index)
|
|
}
|
|
|
|
pub fn write_int_register(&mut self, index: usize, value: i64) {
|
|
self.int_reg.set_reg(index, value);
|
|
}
|
|
|
|
pub fn write_fp_register(&mut self, index: usize, value: f32) {
|
|
self.fp_reg.set_reg(index, value);
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod test {
|
|
use std::fs;
|
|
|
|
use crate::simulator::{machine::Machine, mem_cmp};
|
|
|
|
macro_rules! get_full_path {
|
|
($prefix: expr, $test_name:expr) => {{
|
|
let mut s = String::from("test/machine/");
|
|
s.push_str($prefix);
|
|
s.push_str($test_name);
|
|
s.push_str(".txt");
|
|
&s.to_owned()
|
|
}}
|
|
}
|
|
|
|
macro_rules! init_test {
|
|
($a:expr) => {{
|
|
let mut m = Machine::init_machine();
|
|
let end_file_name = { let mut s = String::from($a); s.push_str("End"); s };
|
|
let memory_before = mem_cmp::MemChecker::from(get_full_path!("memory", $a)).unwrap();
|
|
let memory_after = mem_cmp::MemChecker::from(get_full_path!("memory", &end_file_name)).unwrap();
|
|
mem_cmp::MemChecker::fill_memory_from_mem_checker(&memory_before, &mut m);
|
|
Machine::run(&mut m);
|
|
let expected_trace = fs::read_to_string(get_full_path!("reg_trace", $a)).unwrap();
|
|
(m, memory_after, expected_trace)
|
|
}};
|
|
}
|
|
|
|
#[test]
|
|
fn test_init_machine() {
|
|
let _ = Machine::init_machine();
|
|
}
|
|
|
|
#[test]
|
|
fn test_read_memory() {
|
|
let mut m = Machine::init_machine();
|
|
m.main_memory[4] = 43;
|
|
m.main_memory[5] = 150;
|
|
assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4));
|
|
}
|
|
|
|
#[test]
|
|
fn test_write_memory() {
|
|
let mut m = Machine::init_machine();
|
|
Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
|
|
assert_eq!(43, m.main_memory[6]);
|
|
assert_eq!(150, m.main_memory[7]);
|
|
Machine::write_memory(&mut m, 4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150);
|
|
assert_eq!(52, m.main_memory[8]);
|
|
assert_eq!(20, m.main_memory[9]);
|
|
assert_eq!(43, m.main_memory[10]);
|
|
assert_eq!(150, m.main_memory[11]);
|
|
}
|
|
|
|
#[test]
|
|
fn test_comp() {
|
|
let (m, memory_after, expected_trace) = init_test!("Comp");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_add() {
|
|
let (m, memory_after, expected_trace) = init_test!("Add");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_div() {
|
|
let (m, memory_after, expected_trace) = init_test!("Div");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_if() {
|
|
let (m, memory_after, expected_trace) = init_test!("If");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_jump() {
|
|
let (m, memory_after, expected_trace) = init_test!("Jump");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_mul() {
|
|
let (m, memory_after, expected_trace) = init_test!("Mult");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_ret() {
|
|
let (m, memory_after, expected_trace) = init_test!("Ret");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_sub() {
|
|
let (m, memory_after, expected_trace) = init_test!("Sub");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
|
|
#[test]
|
|
fn test_switch() {
|
|
let (m, memory_after, expected_trace) = init_test!("Switch");
|
|
assert!(mem_cmp::MemChecker::compare_machine_memory(&memory_after, &m));
|
|
assert!(expected_trace.contains(m.registers_trace.as_str()));
|
|
}
|
|
}
|