From f9dba1ac117be2bf8269e3560e9e021943c0c257 Mon Sep 17 00:00:00 2001
From: Moysan Gabriel <gabriel.moysan.1@etudiant.univ-rennes1.fr>
Date: Tue, 15 Nov 2022 21:21:24 +0100
Subject: [PATCH] machine : Instruction type RISCV_OP

---
 src/machine.rs | 75 ++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 70 insertions(+), 5 deletions(-)

diff --git a/src/machine.rs b/src/machine.rs
index 71a2ed5..34bc8df 100644
--- a/src/machine.rs
+++ b/src/machine.rs
@@ -1,10 +1,17 @@
 use crate::decode::*;
 use crate::print::*;
 
+//doit disparaitre
+const MEM_SIZE : usize= 4096;
+
+
 pub struct Machine {
 	pub pc : u32,
 	pub int_reg : [u32 ; 32],
-	pub instructions : [u32 ; 100]
+	pub instructions : [u32 ; 100],
+	pub mainMemory : [u8 ; MEM_SIZE]
+	// futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize;
+	//creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg
 }
 
 
@@ -15,20 +22,26 @@ impl Machine {
 		Machine {
 			pc : 0,
 			instructions : [0 ; 100],
-			int_reg : [0 ; 32]
+			int_reg : [0 ; 32],
+			mainMemory : [0 ; MEM_SIZE]
 		}	
 	}
 
 	pub fn oneInstruction(mut machine : Machine) -> Machine {
+	
+		let mut unsignedReg1 : u64 = 0;
+		let mut unsignedReg2 : u64 = 0;
+	
 		if (machine.instructions.len() <= machine.pc as usize) {
 			println!("ERROR : number max of instructions rushed");
 			return machine;
 		}
 
 		let inst : Instruction = decode(machine.instructions[machine.pc as usize]);
-		machine.pc += 1;
+		
+		machine.pc += 4;
 
-		match (inst.opcode) {
+		match inst.opcode {
 			RISCV_LUI => {
 				machine.int_reg[inst.rd as usize] = inst.imm31_12;
 			},
@@ -36,7 +49,7 @@ impl Machine {
 			//******************************************************************************************
     		// Treatment for: OPI INSTRUCTIONS
 			RISCV_OPI => {
-				match (inst.funct3) {
+				match inst.funct3 {
 					RISCV_OPI_ADDI => {
 						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32;
 					},
@@ -58,6 +71,58 @@ impl Machine {
 					}
 				}
 			},
+			
+			RISCV_JAL => {
+				machine.int_reg[inst.rd as usize] = machine.pc;
+				machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u32);
+			},
+			
+			RISCV_OP => {
+				match inst.funct3 {
+					RISCV_OP_ADD => {
+					// RISCV_OP_ADD_ADD inaccessible
+						/*if (inst.funct7 == RISCV_OP_ADD_ADD) {
+							machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize];*/
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize];
+						//}
+					},
+					RISCV_OP_SLL => {
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f);
+					},
+					RISCV_OP_SLT => {
+						if(machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize]){
+						machine.int_reg[inst.rd as usize] = 1;
+						} else {
+						machine.int_reg[inst.rd as usize] = 0;
+						}
+					},
+					RISCV_OP_SLTU => {
+						unsignedReg1 = machine.int_reg[inst.rs1 as usize] as u64;
+						unsignedReg2 = machine.int_reg[inst.rs2 as usize] as u64;
+						if(unsignedReg1 < unsignedReg2){
+							machine.int_reg[inst.rd as usize] = 1;
+						} else {
+							machine.int_reg[inst.rd as usize] = 0;
+						}
+					},
+					RISCV_OP_XOR => {
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize];
+					},
+					RISCV_OP_SR => {
+					// RISCV_OP_SR_SRL inaccessible
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f);
+					},
+					RISCV_OP_OR => {
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize];
+					},
+					RISCV_OP_AND => {
+						machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize];
+					},
+					_ => {
+						println!("RISCV_OP undefined case\n");
+					}
+				}
+			},
 		}