From f897276c4370e62754a4adc6f916fa1a825e1151 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Wed, 23 Nov 2022 16:29:02 +0100 Subject: [PATCH] change to 64bit --- src/decode.rs | 4 ++-- src/machine.rs | 50 ++++++++++++++++++++++++++++++-------------------- 2 files changed, 32 insertions(+), 22 deletions(-) diff --git a/src/decode.rs b/src/decode.rs index 68d0e2f..32dc030 100644 --- a/src/decode.rs +++ b/src/decode.rs @@ -3,7 +3,7 @@ use core::num::Wrapping; // Permet d'autoriser les overflow pour les opérations #[allow(non_snake_case)] // supprimer le warning snake case (quand les noms de variables ont des majuscules) #[derive(Debug)] pub struct Instruction { - pub value : u32, + pub value : u64, pub opcode : u8, pub rs1 : u8, @@ -31,7 +31,7 @@ pub struct Instruction { } #[allow(non_snake_case)] -pub fn decode(val : u32) -> Instruction { +pub fn decode(val : u64) -> Instruction { let value = val; diff --git a/src/machine.rs b/src/machine.rs index 1d6a0cb..4580ff4 100644 --- a/src/machine.rs +++ b/src/machine.rs @@ -4,13 +4,12 @@ use crate::print::*; // doit disparaitre const MEM_SIZE : usize= 4096; - pub struct Machine { - pub pc : u32, - pub int_reg : [u32 ; 32], - pub instructions : [u32 ; 100], + pub pc : u64, + pub int_reg : [u64 ; 32], + pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], - pub shiftmask : [u32 ; 32] + pub shiftmask : [u64 ; 64] // futur taille à calculer int memSize = g_cfg->NumPhysPages * g_cfg->PageSize; //creer une struct cfg(configuration) qui s'initialise avec valeur dans un fichier cfg } @@ -19,11 +18,11 @@ pub struct Machine { impl Machine { pub fn _init_machine() -> Machine { - let mut shiftmask : [u32 ; 32] = [0 ; 32]; - let mut value : u32 = 0xffff; + let mut shiftmask : [u64 ; 64] = [0 ; 64]; + let mut value : u64 = 0xffffffff; - value = (value << 16) + value; - for i in 0..32 { + value = (value << 32) + value; + for i in 0..64 { shiftmask[i] = value; value = value >> 1; } @@ -78,28 +77,39 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12; + machine.int_reg[inst.rd as usize] = inst.imm31_12 as u64; }, - + RISCV_AUIPC => { + machine.int_reg[inst.rd as usize] = machine.pc - 4 + inst.imm31_12 as u64; + }, + RISCV_JAL => { + machine.int_reg[inst.rd as usize] = machine.pc; + machine.pc += inst.imm21_1_signed as u64 - 4; + }, + RISCV_JALR => { + let tmp = machine.pc; + machine.pc = (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg[inst.rd as usize] = tmp; + } //****************************************************************************************** // Treatment for: OPI INSTRUCTIONS RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as u64; }, RISCV_OPI_SLTI => { machine.int_reg[inst.rd as usize] = - if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u32 { 1 } else { 0 }; + if machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as u64 { 1 } else { 0 }; }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as u64; }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as u64; }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u32; + machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as u64; }, RISCV_OPI_SLLI => { machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; @@ -117,7 +127,7 @@ impl Machine { RISCV_JAL => { machine.int_reg[inst.rd as usize] = machine.pc; - machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u32); + machine.pc = machine.pc - 4 + (inst.imm21_1_signed as u64); }, RISCV_OP => { @@ -125,7 +135,7 @@ impl Machine { match inst.funct3 { RISCV_OP_M_MUL => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; - machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as u64; }, RISCV_OP_M_MULH => { long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; @@ -134,7 +144,7 @@ impl Machine { RISCV_OP_M_MULHSU => { unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; }, // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve /* @@ -145,7 +155,7 @@ impl Machine { unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; long_result = (unsigned_reg1 * unsigned_reg2) as i128; - machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u32; + machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as u64; }, RISCV_OP_M_DIV => { machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]);