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♻️ Error management and simplification

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Modified methods
 - load_instruction
  - store_instruction
This commit is contained in:
François Autin 2023-03-25 15:57:28 +01:00
parent 3dfeca4c42
commit e77e125f96
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 15 additions and 23 deletions
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38
src/simulator/machine.rs
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@ -340,47 +340,39 @@ impl Machine {
/// Executes RISC-V Load Instructions on the machine
fn load_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut set_reg = |rd, size| {
let val = self.read_memory(size, (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64;
self.int_reg.set_reg(rd, val);
Ok(())
};
match inst.funct3 {
RISCV_LD_LB | RISCV_LD_LBU => {
let tmp = self.read_memory(1, (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64;
self.int_reg.set_reg(inst.rd, tmp);
},
RISCV_LD_LH | RISCV_LD_LHU => {
let tmp = self.read_memory(2, (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64;
self.int_reg.set_reg(inst.rd, tmp);
},
RISCV_LD_LW | RISCV_LD_LWU => {
let tmp = self.read_memory(4, (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64;
self.int_reg.set_reg(inst.rd, tmp);
},
RISCV_LD_LD => {
let tmp = self.read_memory(8, (self.int_reg.get_reg(inst.rs1) + inst.imm12_I_signed as i64) as usize) as i64;
self.int_reg.set_reg(inst.rd, tmp);
},
_ => panic!("In LD switch case, this should never happen... Instr was {}", inst.value)
RISCV_LD_LB | RISCV_LD_LBU => set_reg(inst.rd, 1),
RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2),
RISCV_LD_LW | RISCV_LD_LWU => set_reg(inst.rd, 4),
RISCV_LD_LD => set_reg(inst.rd, 8),
_ => Err(MachineError::new(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str()))
}
Ok(())
}
/// Executes RISC-V Store Instructions on the machine
fn store_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut store = |size|
let mut store = |size| {
self.write_memory(
size,
(self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize,
self.int_reg.get_reg(inst.rs2) as u64
);
Ok(())
};
match inst.funct3 {
RISCV_ST_STB => store(1),
RISCV_ST_STH => store(2),
RISCV_ST_STW => store(4),
RISCV_ST_STD => store(8),
_ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value)
_ => Err(MachineError::new(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str()))
}
Ok(())
}
/// Executes RISC-V Integer Register-Immediate Instructions on the machine