From 46752df2c90292499dfee261ddba86582e6ec165 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Thu, 26 Jan 2023 00:02:22 +0100 Subject: [PATCH 1/4] Add a first implementation to fix register zero issue --- src/simulator/machine.rs | 59 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 83be4a4..31e4993 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -1,8 +1,61 @@ +use std::ops::{Add, Sub}; + use super::{decode::{Instruction, decode}}; use super::global::*; /// doit disparaitre const MEM_SIZE : usize = 4096; +trait RegisterNum: Add + Sub + PartialEq + Copy {} + +impl RegisterNum for i64 {} + +impl RegisterNum for f32 {} + +struct Register { + register: [U; 32] +} + +impl Register { + + pub fn get_reg(&self, position: usize) -> U { + self.register[position] + } + +} + +impl Register { + + pub fn init() -> Register { + Register { + register: [0i64; 32] + } + } + + pub fn write_reg(&mut self, position: usize, value: i64) { + if position != 0 { + self.register[position] = value; + } else { + // Panic ou rien ? (dans le doute pour le moment panic) + unreachable!("You can't write to zero register") + } + } + +} + +impl Register { + + pub fn init() -> Register { + Register { + register: [0f32; 32] + } + } + + pub fn write_reg(&mut self, position: usize, value: f32) { + self.register[position] = value; + } + +} + pub struct Machine { pub pc : u64, pub int_reg : [i64 ; 32], @@ -26,13 +79,17 @@ impl Machine { value >>= 1; } + // let int_reg = Register::::init(); + // let fp_reg = Register::::init(); + Machine { pc : 0, instructions : [0 ; 100], int_reg : [0 ; 32], main_memory : [0 ; MEM_SIZE], shiftmask - } + } + } /// Read from main memory of the machine From 86ab1161e7879aa8d59b664dcf03bbf93ee50c1a Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Thu, 26 Jan 2023 00:08:49 +0100 Subject: [PATCH 2/4] function name more consistent --- src/simulator/machine.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 31e4993..e336842 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -31,7 +31,7 @@ impl Register { } } - pub fn write_reg(&mut self, position: usize, value: i64) { + pub fn set_reg(&mut self, position: usize, value: i64) { if position != 0 { self.register[position] = value; } else { @@ -50,7 +50,7 @@ impl Register { } } - pub fn write_reg(&mut self, position: usize, value: f32) { + pub fn set_reg(&mut self, position: usize, value: f32) { self.register[position] = value; } From 72b2a105f01af012c21e1a67a9f07c5b04d65bb7 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Fri, 27 Jan 2023 11:15:39 +0100 Subject: [PATCH 3/4] Add tests to machine --- src/simulator/machine.rs | 68 ++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 9 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e336842..26f4eae 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -139,10 +139,9 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions - pub fn run(machine : Machine){ - let mut m = machine; - loop{ - Machine::one_instruction(&mut m); + pub fn run(&mut self){ + loop { + self.one_instruction(); } } @@ -151,8 +150,8 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions and a pc to the actual instruction - pub fn one_instruction(machine :&mut Machine) { - + pub fn one_instruction(&mut self) { + let mut machine = self; let unsigned_reg1 : u64; let unsigned_reg2 : u64; let long_result : i128; @@ -466,11 +465,21 @@ impl Machine { #[cfg(test)] mod test { - use crate::simulator::machine::Machine; + use crate::simulator::{machine::Machine, decode}; + + + fn init() -> Machine { + let mut m = Machine::_init_machine(); + m.main_memory[0] = 255; + m.main_memory[1] = 43; + m.main_memory[2] = 7; + m.main_memory[3] = 157; + m + } #[test] fn test_read_memory() { - let mut m = Machine::_init_machine(); + let mut m = init(); m.main_memory[4] = 43; m.main_memory[5] = 150; assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); @@ -478,9 +487,50 @@ impl Machine { #[test] fn test_write_memory() { - let mut m = Machine::_init_machine(); + let mut m = init(); Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); assert_eq!(43, m.main_memory[6]); assert_eq!(150, m.main_memory[7]); } + + #[test] + fn test_op_add() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b0000000_00110_00000_000_00101_0110011; + // add t0, zero, t1 + m.one_instruction(); + assert_eq!(m.int_reg[5], 5); + } + + #[test] + fn test_op_sub() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b0100000_00110_00000_000_00101_0110011; + // sub t0, zero, t1 + m.one_instruction(); + assert_eq!(m.int_reg[5], -5); + } + + #[test] + fn test_op_addi() { + let mut m = init(); + m.int_reg[6] = 5; // t1 + m.instructions[0] = 0b11111111111_00110_000_00101_0010011; + // add t0, t1, 2047 + m.one_instruction(); + assert_eq!(m.int_reg[5], 2052); + } + + /// Equivalent of subi + #[test] + fn test_op_addi_neg() { + let mut m = init(); + m.int_reg[6] = -5; // t1 + m.instructions[0] = 0b11111111111_00110_000_00101_0010011; + // addi t0, t1, 2047 + m.one_instruction(); + assert_eq!(m.int_reg[5], 2042); + } } From 5ad42a7073a5e42fc25169d9a2bed204583ba5b5 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 14:30:36 +0100 Subject: [PATCH 4/4] Revert "Add tests to machine" This reverts commit 72b2a105f01af012c21e1a67a9f07c5b04d65bb7. --- src/simulator/machine.rs | 68 ++++++---------------------------------- 1 file changed, 9 insertions(+), 59 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index 26f4eae..e336842 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -139,9 +139,10 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions - pub fn run(&mut self){ - loop { - self.one_instruction(); + pub fn run(machine : Machine){ + let mut m = machine; + loop{ + Machine::one_instruction(&mut m); } } @@ -150,8 +151,8 @@ impl Machine { /// ### Parameters /// /// - **machine** which contains a table of instructions and a pc to the actual instruction - pub fn one_instruction(&mut self) { - let mut machine = self; + pub fn one_instruction(machine :&mut Machine) { + let unsigned_reg1 : u64; let unsigned_reg2 : u64; let long_result : i128; @@ -465,21 +466,11 @@ impl Machine { #[cfg(test)] mod test { - use crate::simulator::{machine::Machine, decode}; - - - fn init() -> Machine { - let mut m = Machine::_init_machine(); - m.main_memory[0] = 255; - m.main_memory[1] = 43; - m.main_memory[2] = 7; - m.main_memory[3] = 157; - m - } + use crate::simulator::machine::Machine; #[test] fn test_read_memory() { - let mut m = init(); + let mut m = Machine::_init_machine(); m.main_memory[4] = 43; m.main_memory[5] = 150; assert_eq!((43 << 8) + 150, Machine::read_memory(&mut m, 2, 4)); @@ -487,50 +478,9 @@ impl Machine { #[test] fn test_write_memory() { - let mut m = init(); + let mut m = Machine::_init_machine(); Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150); assert_eq!(43, m.main_memory[6]); assert_eq!(150, m.main_memory[7]); } - - #[test] - fn test_op_add() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b0000000_00110_00000_000_00101_0110011; - // add t0, zero, t1 - m.one_instruction(); - assert_eq!(m.int_reg[5], 5); - } - - #[test] - fn test_op_sub() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b0100000_00110_00000_000_00101_0110011; - // sub t0, zero, t1 - m.one_instruction(); - assert_eq!(m.int_reg[5], -5); - } - - #[test] - fn test_op_addi() { - let mut m = init(); - m.int_reg[6] = 5; // t1 - m.instructions[0] = 0b11111111111_00110_000_00101_0010011; - // add t0, t1, 2047 - m.one_instruction(); - assert_eq!(m.int_reg[5], 2052); - } - - /// Equivalent of subi - #[test] - fn test_op_addi_neg() { - let mut m = init(); - m.int_reg[6] = -5; // t1 - m.instructions[0] = 0b11111111111_00110_000_00101_0010011; - // addi t0, t1, 2047 - m.one_instruction(); - assert_eq!(m.int_reg[5], 2042); - } }