Register name convention
This commit is contained in:
parent
98f4c0b67e
commit
dcd2012c64
131
src/print.rs
131
src/print.rs
@ -138,11 +138,24 @@ const names_br: [&str; 8] = ["beq", "bne", "", "", "blt", "bge", "bltu", "bgeu"]
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const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"];
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const names_st: [&str; 4] = ["sb", "sh", "sw", "sd"];
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const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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const names_ld: [&str; 7] = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"];
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const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
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const names_opw: [&str; 8] = ["addw", "sllw", "", "", "", "srw", "", ""];
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const names_opiw: [&str; 8] = ["addwi", "sllwi", "", "", "", "sri", "", ""];
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const names_opiw: [&str; 8] = ["addiw", "slliw", "", "", "", "sri", "", ""];
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// Register name mapping
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const reg_x: [&str; 32] = ["zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", // fp ou s0 ?
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"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"];
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const _reg_f: [&str; 32] = ["ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
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"fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
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"fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11",
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"ft8", "ft9", "ft10", "ft11"];
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pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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let rd = ins.rd as usize;
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let rs1 = ins.rs1 as usize;
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let rs2 = ins.rs2 as usize;
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match ins.opcode {
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match ins.opcode {
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RISCV_OP => {
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RISCV_OP => {
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@ -168,33 +181,33 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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name = names_op[ins.funct3 as usize];
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name = names_op[ins.funct3 as usize];
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}
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}
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}
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}
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format!("{} r{}, r{}, r{}", name.to_string(), &ins.rd.to_string(), &ins.rs1.to_string(), &ins.rs2.to_string())
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format!("{} {}, {}, {}", name.to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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},
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},
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RISCV_OPI => {
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RISCV_OPI => {
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// SHAMT OR IMM
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// SHAMT OR IMM
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if ins.funct3 == RISCV_OPI_SRI {
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if ins.funct3 == RISCV_OPI_SRI {
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if ins.funct7 == RISCV_OPI_SRI_SRLI {
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if ins.funct7 == RISCV_OPI_SRI_SRLI {
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format!("slrii x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string())
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format!("slrii {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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} else {
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} else {
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format!("srai x{}, x{}, {}", ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string())
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format!("srai {}, {}, {}", reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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}
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}
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} else if ins.funct3 == RISCV_OPI_SLLI {
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} else if ins.funct3 == RISCV_OPI_SLLI {
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format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.shamt.to_string())
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.shamt.to_string())
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} else {
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} else {
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format!("{} x{}, x{}, {}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string())
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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}
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}
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},
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},
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RISCV_LUI => {
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RISCV_LUI => {
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format!("lui x{}, 0x{:X}", ins.rd.to_string(), ins.imm31_12)
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format!("lui {}, 0x{:X}", reg_x[rd], ins.imm31_12)
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},
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},
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RISCV_AUIPC => {
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RISCV_AUIPC => {
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format!("auipc x{}, {:X}", ins.rd.to_string(), ins.imm31_12)
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format!("auipc {}, {:X}", reg_x[rd], ins.imm31_12)
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},
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},
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RISCV_JAL => {
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RISCV_JAL => {
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if ins.rd == 0 {
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if ins.rd == 0 {
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format!("j {}", ins.imm31_12.to_string())
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format!("j {}", ins.imm31_12.to_string())
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} else {
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} else {
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format!("jal x{}, {:X}", ins.rd.to_string(), (pc - 4 + ins.imm21_1_signed))
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format!("jal {}, {:X}", reg_x[rd], (pc - 4 + ins.imm21_1_signed))
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}
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}
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},
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},
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RISCV_JALR => {
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RISCV_JALR => {
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@ -205,49 +218,49 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
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format!("jr {:X}", ins.imm31_12)
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format!("jr {:X}", ins.imm31_12)
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}
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}
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} else {
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} else {
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format!("jalr {}, (r{})", ins.imm12_I_signed.to_string(), ins.rs1.to_string())
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format!("jalr {}, ({})", ins.imm12_I_signed.to_string(), reg_x[rs1])
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}
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}
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},
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},
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RISCV_BR => {
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RISCV_BR => {
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format!("{} r{} x{} {}", names_br[ins.funct3 as usize].to_string(), ins.rs1.to_string(), ins.rs2.to_string(), ins.imm13_signed.to_string())
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format!("{} {}, {}, {}", names_br[ins.funct3 as usize].to_string(), reg_x[rs1], reg_x[rs2], ins.imm13_signed.to_string())
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},
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},
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RISCV_LD => {
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RISCV_LD => {
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format!("{} x{}, {}(x{})", names_ld[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.imm12_I_signed.to_string(), ins.rs1.to_string())
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format!("{} {}, {}({})", names_ld[ins.funct3 as usize].to_string(), reg_x[rd], ins.imm12_I_signed.to_string(), reg_x[rs1])
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},
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},
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RISCV_ST => {
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RISCV_ST => {
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format!("{} x{}, {}(x{})", names_st[ins.funct3 as usize].to_string(), ins.rs2.to_string(), ins.imm12_S_signed.to_string(), ins.rs1.to_string())
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format!("{} {}, {}({})", names_st[ins.funct3 as usize].to_string(), reg_x[rs2], ins.imm12_S_signed.to_string(), reg_x[rs1])
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},
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},
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RISCV_OPIW => {
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RISCV_OPIW => {
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if ins.funct3 == RISCV_OPIW_SRW {
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if ins.funct3 == RISCV_OPIW_SRW {
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if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
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if ins.funct7 == RISCV_OPIW_SRW_SRLIW {
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format!("srlwi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("srlwi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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} else {
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format!("srawi x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("srawi {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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}
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} else if ins.funct3 == RISCV_OPIW_SLLIW {
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} else if ins.funct3 == RISCV_OPIW_SLLIW {
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format!("{} x{}, x{}, x{}", names_opi[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("{} {}, {}, {}", names_opi[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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} else {
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format!("{} x{}, x{}, x{}", names_opiw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.imm12_I_signed.to_string())
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format!("{} {}, {}, {}", names_opiw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], ins.imm12_I_signed.to_string())
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}
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}
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},
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},
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RISCV_OPW => {
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RISCV_OPW => {
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if ins.funct7 == 1 {
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if ins.funct7 == 1 {
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format!("{}w x{}, x{}, x{}", names_mul[ins.funct3 as usize].to_string(), ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("{}w {}, {}, {}", names_mul[ins.funct3 as usize].to_string(), reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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} else {
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if ins.funct3 == RISCV_OP_ADD {
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if ins.funct3 == RISCV_OP_ADD {
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if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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if ins.funct7 == RISCV_OPW_ADDSUBW_ADDW {
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format!("addw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("addw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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} else {
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format!("subw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("subw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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}
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} else if ins.funct3 == RISCV_OPW_SRW {
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} else if ins.funct3 == RISCV_OPW_SRW {
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if ins.funct7 == RISCV_OPW_SRW_SRLW {
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if ins.funct7 == RISCV_OPW_SRW_SRLW {
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format!("srlw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("srlw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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} else {
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} else {
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format!("sraw x{}, x{}, x{}", ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("sraw {}, {}, {}", reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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}
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} else {
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} else {
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format!("{} x{}, x{}, x{}", names_opw[ins.funct3 as usize], ins.rd.to_string(), ins.rs1.to_string(), ins.rs2.to_string())
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format!("{} {}, {}, {}", names_opw[ins.funct3 as usize], reg_x[rd], reg_x[rs1], reg_x[rs2])
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}
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}
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}
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}
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},
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},
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@ -273,11 +286,11 @@ mod test {
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let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
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let slr = decode::decode(0b0000000_10000_10001_101_11100_0110011);
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let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
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let sra = decode::decode(0b0100000_10000_10001_101_11100_0110011);
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assert_eq!("sub r28, r17, r16", print::print(sub, 0));
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assert_eq!("sub t3, a7, a6", print::print(sub, 0));
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assert_eq!("xor r28, r17, r16", print::print(xor, 0));
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assert_eq!("xor t3, a7, a6", print::print(xor, 0));
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assert_eq!("srl r28, r17, r16", print::print(slr, 0));
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assert_eq!("srl t3, a7, a6", print::print(slr, 0));
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assert_eq!("sra r28, r17, r16", print::print(sra, 0));
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assert_eq!("sra t3, a7, a6", print::print(sra, 0));
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assert_eq!("add r28, r17, r16", print::print(add, 0));
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assert_eq!("add t3, a7, a6", print::print(add, 0));
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}
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}
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@ -290,21 +303,21 @@ mod test {
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let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
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let xori = decode::decode(0b_0000000000010001_100_11100_0010011);
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let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
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let ori = decode::decode(0b00000000000_10001_110_11100_0010011);
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let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
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let andi = decode::decode(0b000000000000_10001_111_11100_0010011);
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assert_eq!("andi x28, x17, 0", print::print(andi, 0));
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assert_eq!("andi t3, a7, 0", print::print(andi, 0));
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assert_eq!("addi x28, x17, 0", print::print(addi, 0));
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assert_eq!("addi t3, a7, 0", print::print(addi, 0));
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assert_eq!("slli x28, x17, 0", print::print(slli, 0));
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assert_eq!("slli t3, a7, 0", print::print(slli, 0));
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assert_eq!("slti x28, x17, 0", print::print(slti, 0));
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assert_eq!("slti t3, a7, 0", print::print(slti, 0));
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assert_eq!("sltiu x28, x17, 0", print::print(sltiu, 0));
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assert_eq!("sltiu t3, a7, 0", print::print(sltiu, 0));
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assert_eq!("xori x28, x17, 0", print::print(xori, 0));
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assert_eq!("xori t3, a7, 0", print::print(xori, 0));
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assert_eq!("ori x28, x17, 0", print::print(ori, 0));
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assert_eq!("ori t3, a7, 0", print::print(ori, 0));
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}
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}
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#[test]
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#[test]
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fn test_lui() {
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fn test_lui() {
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let lui = decode::decode(0b01110001000011111000_11100_0110111);
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let lui = decode::decode(0b01110001000011111000_11100_0110111);
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let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
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let lui_negatif = decode::decode(0b11110001000011111000_11100_0110111);
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assert_eq!("lui x28, 0x710F8000", print::print(lui, 0));
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assert_eq!("lui t3, 0x710F8000", print::print(lui, 0));
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assert_eq!("lui x28, 0xF10F8000", print::print(lui_negatif, 0));
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assert_eq!("lui t3, 0xF10F8000", print::print(lui_negatif, 0));
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}
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}
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#[test]
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#[test]
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@ -318,13 +331,13 @@ mod test {
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let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
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let ld = decode::decode(0b010111110000_10001_011_11100_0000011);
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let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
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let lwu = decode::decode(0b010111110000_10001_110_11100_0000011);
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// TODO: imm négatif produit une erreur
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// TODO: imm négatif produit une erreur
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assert_eq!("lb x28, 1520(x17)", print::print(lb, 0));
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assert_eq!("lb t3, 1520(a7)", print::print(lb, 0));
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assert_eq!("lh x28, 1520(x17)", print::print(lh, 0));
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assert_eq!("lh t3, 1520(a7)", print::print(lh, 0));
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assert_eq!("lw x28, 1520(x17)", print::print(lw, 0));
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assert_eq!("lw t3, 1520(a7)", print::print(lw, 0));
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assert_eq!("lbu x28, 1520(x17)", print::print(lbu, 0));
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assert_eq!("lbu t3, 1520(a7)", print::print(lbu, 0));
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assert_eq!("lhu x28, 1520(x17)", print::print(lhu, 0));
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assert_eq!("lhu t3, 1520(a7)", print::print(lhu, 0));
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assert_eq!("ld x28, 1520(x17)", print::print(ld, 0));
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assert_eq!("ld t3, 1520(a7)", print::print(ld, 0));
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assert_eq!("lwu x28, 1520(x17)", print::print(lwu, 0));
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assert_eq!("lwu t3, 1520(a7)", print::print(lwu, 0));
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}
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}
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#[test]
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#[test]
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@ -334,20 +347,20 @@ mod test {
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let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
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let srlw: decode::Instruction = decode::decode(0b0000000_10000_10001_101_11100_0111011);
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let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
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let sraw: decode::Instruction = decode::decode(0b0100000_10000_10001_101_11100_0111011);
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assert_eq!("addw x28, x17, x16", print::print(addw, 0));
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assert_eq!("addw t3, a7, a6", print::print(addw, 0));
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assert_eq!("sllw x28, x17, x16", print::print(sllw, 0));
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assert_eq!("sllw t3, a7, a6", print::print(sllw, 0));
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assert_eq!("srlw x28, x17, x16", print::print(srlw, 0));
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assert_eq!("srlw t3, a7, a6", print::print(srlw, 0));
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assert_eq!("sraw x28, x17, x16", print::print(sraw, 0));
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assert_eq!("sraw t3, a7, a6", print::print(sraw, 0));
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}
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}
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#[test]
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#[test]
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fn test_opwi() {
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fn test_opwi() {
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let addwi: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
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let addiw: decode::Instruction =decode::decode(0b000000000000_10001_000_11100_0011011);
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let sllwi: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
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let slliw: decode::Instruction = decode::decode(0b0000000_10000_10001_001_11100_0011011);
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let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
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let srai: decode::Instruction = decode::decode(0b010000010001_10001_101_11100_0010011);
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assert_eq!("addwi x28, x17, x0", print::print(addwi, 0));
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assert_eq!("addiw t3, a7, 0", print::print(addiw, 0));
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assert_eq!("slli x28, x17, x16", print::print(sllwi, 0));
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assert_eq!("slli t3, a7, a6", print::print(slliw, 0));
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assert_eq!("srai x28, x17, 17", print::print(srai, 0));
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assert_eq!("srai t3, a7, 17", print::print(srai, 0));
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -359,12 +372,12 @@ mod test {
|
|||||||
let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
|
let bge: decode::Instruction = decode::decode(0b0000000_10000_10001_101_00000_1100011);
|
||||||
let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
|
let bltu: decode::Instruction = decode::decode(0b0000000_10000_10001_110_00000_1100011);
|
||||||
let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
|
let bgeu: decode::Instruction = decode::decode(0b0000000_10000_10001_111_00000_1100011);
|
||||||
assert_eq!("blt r17 x16 0", print::print(blt, 0));
|
assert_eq!("blt a7, a6, 0", print::print(blt, 0));
|
||||||
assert_eq!("bge r17 x16 0", print::print(bge, 0));
|
assert_eq!("bge a7, a6, 0", print::print(bge, 0));
|
||||||
assert_eq!("bltu r17 x16 0", print::print(bltu, 0));
|
assert_eq!("bltu a7, a6, 0", print::print(bltu, 0));
|
||||||
assert_eq!("bgeu r17 x16 0", print::print(bgeu, 0));
|
assert_eq!("bgeu a7, a6, 0", print::print(bgeu, 0));
|
||||||
assert_eq!("bne r17 x16 0", print::print(bne, 0));
|
assert_eq!("bne a7, a6, 0", print::print(bne, 0));
|
||||||
assert_eq!("beq r17 x16 0", print::print(beq, 0));
|
assert_eq!("beq a7, a6, 0", print::print(beq, 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
Loading…
Reference in New Issue
Block a user