From d352f5dcd2f0dfa1cc698d452e9e0c00fd896692 Mon Sep 17 00:00:00 2001 From: Baptiste Date: Mon, 6 Mar 2023 13:50:45 +0100 Subject: [PATCH] fix jal, branch instr & LD. + better print for machine status --- src/main.rs | 2 +- src/simulator/machine.rs | 34 +++++++++++++++++++++++----------- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/main.rs b/src/main.rs index d33c4dc..2acab96 100644 --- a/src/main.rs +++ b/src/main.rs @@ -5,7 +5,7 @@ use simulator::mem_cmp; fn main() { let mut m = Machine::_init_machine(); - let path = "memoryComp.txt".to_string(); + let path = "memoryJump.txt".to_string(); let checker = mem_cmp::Mem_Checker::from(&path); mem_cmp::Mem_Checker::fill_memory_from_Mem_Checker(&checker, &mut m); //mem_cmp::Mem_Checker::print_Mem_Checker(&checker); diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index c3a5659..2baf432 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -152,9 +152,21 @@ impl Machine { pub fn print_machine_status(machine: &mut Machine) { println!("######### Machine status #########"); - for i in 0..32 { - println!(">{} : {:x}", print::REG_X[i], machine.int_reg.get_reg(i)); + for i in (0..32).step_by(3) { + print!(">{0: <4} : {1:<8x}", print::REG_X[i], machine.int_reg.get_reg(i)); + print!("\t"); + print!(">{0: <4} : {1:<8x}", print::REG_X[i+1], machine.int_reg.get_reg(i+1)); + print!("\t"); + if i+2 < 32 { + print!(">{0: <4} : {1:<8x}", print::REG_X[i+2], machine.int_reg.get_reg(i+2)); + } + println!(); } + println!("________________SP________________"); + let sp_index = machine.int_reg.get_reg(2); + for i in 0..5 { + println!("SP+{:<2} : {:16x}", i*8, Self::read_memory(machine, 8, (sp_index + i*8) as usize)); + } println!("##################################"); } @@ -213,11 +225,11 @@ impl Machine { }, RISCV_JAL => { machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); - machine.pc += inst.imm21_1_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm21_1_signed as i64 - 4) as u64; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as u64 & 0xfffffffe; machine.int_reg.set_reg(inst.rd as usize, tmp as i64); }, @@ -227,32 +239,32 @@ impl Machine { match inst.funct3 { RISCV_BR_BEQ => { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BNE => { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLT => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGE => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BLTU => { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, RISCV_BR_BGEU => { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { - machine.pc += inst.imm13_signed as u64 - 4; + machine.pc = (machine.pc as i64 + inst.imm13_signed as i64 - 4) as u64; } }, _ => { @@ -278,7 +290,7 @@ impl Machine { machine.int_reg.set_reg(inst.rd as usize, tmp); }, RISCV_LD_LD => { - let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; + let tmp = Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, tmp); }, _ => {